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Changed instruction size opcode bits
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@rherveille
rherveille committed Mar 18, 2024
1 parent 3855635 commit f3c3668
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Showing 6 changed files with 116 additions and 174 deletions.
4 changes: 2 additions & 2 deletions rtl/verilog/core/ex/riscv_alu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -133,8 +133,8 @@ import riscv_state_pkg::*;
casex ( {xlen32, opcR} )
{1'b?,LUI }: alu_r_o <= opA_i + opB_i; //actually just opB_i, but simplify encoding
{1'b?,AUIPC }: alu_r_o <= opA_i + opB_i;
{1'b?,JAL }: alu_r_o <= id_pc_i + (&id_insn_i.instr[1:0] || !has_rvc ? 'h4 : 'h2);
{1'b?,JALR }: alu_r_o <= id_pc_i + (&id_insn_i.instr[1:0] || !has_rvc ? 'h4 : 'h2);
{1'b?,JAL }: alu_r_o <= id_pc_i + ('h2 << id_insn_i.instr[1:0]);
{1'b?,JALR }: alu_r_o <= id_pc_i + ('h2 << id_insn_i.instr[1:0]);

//logical operators
{1'b?,ADDI }: alu_r_o <= opA_i + opB_i;
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18 changes: 9 additions & 9 deletions rtl/verilog/core/ex/riscv_bu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -213,7 +213,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i +(is_16bit_instruction ? 'h2 : 'h4);
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
{1'b0,BNE }: begin
bu_bubble = 1'b0;
Expand All @@ -224,7 +224,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + (is_16bit_instruction ? 'h2 : 'h4);
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
{1'b0,BLTU }: begin
bu_bubble = 1'b0;
Expand All @@ -235,7 +235,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
{1'b0,BGEU }: begin
bu_bubble = 1'b0;
Expand All @@ -246,7 +246,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i +'h4;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
{1'b0,BLT }: begin
bu_bubble = 1'b0;
Expand All @@ -257,7 +257,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
{1'b0,BGE }: begin
bu_bubble = 1'b0;
Expand All @@ -268,7 +268,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
{1'b0,MISCMEM}: case (id_insn_i.instr)
FENCE_I: begin
Expand All @@ -280,7 +280,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b1;
dc_invalidate = 1'b0;
dc_clean = 1'b1;
nxt_pc = id_pc_i +'h4;
nxt_pc = id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
default: begin
bu_bubble = 1'b1;
Expand All @@ -291,7 +291,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = id_pc_i + 'h4;
nxt_pc = id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
endcase
default : begin
Expand All @@ -303,7 +303,7 @@ import riscv_state_pkg::*;
ic_invalidate = 1'b0;
dc_invalidate = 1'b0;
dc_clean = 1'b0;
nxt_pc = id_pc_i + (is_16bit_instruction ? 'h2 : 'h4);
nxt_pc = id_pc_i + ('h2 << id_insn_i.instr.SB.size);
end
endcase

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34 changes: 20 additions & 14 deletions rtl/verilog/core/riscv_id.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -295,6 +295,9 @@ import riscv_state_pkg::*;
*
* TODO: push if-instr upon illegal-instruction
*/
assign id_insn_o.retired = 1'b0;


always @(posedge clk_i)
if (!stalls) id_insn_o.instr <= pd_insn_i.instr;

Expand All @@ -309,15 +312,17 @@ import riscv_state_pkg::*;
else if ( bu_flush_i || st_flush_i) id_bubble_r <= 1'b1;
else if (!stalls ) id_bubble_r <= pd_insn_i.bubble | id_stall_o | my_exceptions.any;


//local stall
assign stalls = ex_stall_i;
assign flushes = bu_flush_i | st_flush_i;
assign exceptions = ex_exceptions_i.any | mem_exceptions_i.any | wb_exceptions_i.any;
assign id_insn_o.bubble = stalls | flushes | exceptions | id_bubble_r;


assign is_32bit_instruction = ~&pd_insn_i.instr[4:2] & &pd_insn_i.instr[1:0];
//This is the correct decoder for a 32bit instruction. But we change this in IF
// assign is_32bit_instruction = ~&pd_insn_i.instr[4:2] & &pd_insn_i.instr[1:0];
assign is_32bit_instruction = ~&pd_insn_i.instr[4:1] & pd_insn_i.instr[0];

assign pd_opcR = decode_opcR(pd_insn_i.instr);

Expand Down Expand Up @@ -947,13 +952,14 @@ endgenerate
//ALU
always_comb
casex (pd_insn_i.instr)
FENCE : illegal_alu_instr = ~is_32bit_instruction;
FENCE_I: illegal_alu_instr = ~is_32bit_instruction;
ECALL : illegal_alu_instr = ~is_32bit_instruction;
EBREAK : illegal_alu_instr = ~is_32bit_instruction & ~has_rvc;
URET : illegal_alu_instr = ~is_32bit_instruction | ~has_u;
SRET : illegal_alu_instr = ~is_32bit_instruction | ~has_s | (st_prv_i < PRV_S) | (st_prv_i == PRV_S && st_tsr_i);
MRET : illegal_alu_instr = ~is_32bit_instruction | (st_prv_i != PRV_M);
FENCE : illegal_alu_instr = 1'b0;
FENCE_I: illegal_alu_instr = 1'b0;
ECALL : illegal_alu_instr = 1'b0;
EBREAK : illegal_alu_instr = 1'b0;
EBREAKC: illegal_alu_instr = ~has_rvc;
URET : illegal_alu_instr = ~has_u;
SRET : illegal_alu_instr = ~has_s | (st_prv_i < PRV_S) | (st_prv_i == PRV_S && st_tsr_i);
MRET : illegal_alu_instr = (st_prv_i != PRV_M);
default:
casex ( {xlen32,pd_opcR} )
{1'b?,LUI }: illegal_alu_instr = ~is_32bit_instruction & ~has_rvc;
Expand Down Expand Up @@ -997,11 +1003,11 @@ endgenerate

//system
{1'b?,CSRRW }: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | illegal_csr_wr;
{1'b?,CSRRS }: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr) | ~is_32bit_instruction;
{1'b?,CSRRC }: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr) | ~is_32bit_instruction;
{1'b?,CSRRWI}: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr) | ~is_32bit_instruction;
{1'b?,CSRRSI}: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr) | ~is_32bit_instruction;
{1'b?,CSRRCI}: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr) | ~is_32bit_instruction;
{1'b?,CSRRS }: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr);
{1'b?,CSRRC }: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr);
{1'b?,CSRRWI}: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr);
{1'b?,CSRRSI}: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr);
{1'b?,CSRRCI}: illegal_alu_instr = ~is_32bit_instruction | illegal_csr_rd | (|pd_rs1 & illegal_csr_wr);

default: illegal_alu_instr = 1'b1;
endcase
Expand Down
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