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v1.1: RV12 32/64 Bit RISC-V CPU - Initial Release
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@sphardy sphardy released this 01 Nov 12:22
· 530 commits to master since this release
v1.1
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sphardy Paul H
GPG key ID: 25CEB9FE915DD620
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Summary

Description

Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.

Optional features

  • Branch Prediction
  • Instruction and Data Caches
  • Data Cache

Parameterised and configurable features

  • Instruction and data interfaces
  • Branch-prediction-unit configuration
  • Cache size, associativity, and replacement algorithms.

Release Notes:

  • First Full Source Code & Documentation Release for Roa Logic RV12 CPU
  • Full Support for Privileged Spec v1.9.1 and User Spec v 2.2
  • See Roa Logic Web Site for more information
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