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v1.2: RV12 32/64 Bit RISC-V CPU - Bug Fix #1
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@sphardy sphardy released this 24 Nov 13:50
· 529 commits to master since this release
v1.2
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sphardy Paul H
GPG key ID: 25CEB9FE915DD620
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Summary

Description

Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.

New Features

  • None

Release Notes / Bug Fixes

  • Remove README reference to Wishbone Interface (Not yet added to core)
  • Remove spurious swap files from respository

(Datasheet unchanged, remains at v1.1)

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