Merge branch 'swim-v2' of github.com:SWIM-ucf/SWIM into riscv-string-…

…version

src/agent.rs

@@ -159,6 +159,11 @@ pub async fn emulation_core_agent(scope: ReactorScope<Command, DatapathUpdate>)
                         state.updates.changed_stack,
                         RiscStateUpdate::UpdateStack(datapath.stack.clone())
                     );
+                    send_update_riscv!(
+                        state.scope,
+                        state.updates.changed_coprocessor_registers,
+                        RiscStateUpdate::UpdateCoprocessorRegisters(datapath.coprocessor.registers)
+                    );
                 }
             }
             state.updates = Default::default();
@@ -304,7 +309,7 @@ impl EmulatorCoreAgentState {
             DatapathRef::MIPS(datapath) => datapath.registers.pc,
             DatapathRef::RISCV(datapath) => datapath.registers.pc,
         };
-        if self.breakpoints.contains(&current_pc) && self.updates.hit_breakpoint {
+        if self.breakpoints.contains(&current_pc) || self.updates.hit_breakpoint {
             self.executing = false;
             // Unset the hit_breakpoint flag after processing
             self.updates.hit_breakpoint = false;

src/agent/datapath_reducer.rs

@@ -8,7 +8,9 @@ use crate::emulation_core::mips::gp_registers::{GpRegisterType, GpRegisters};
 use crate::emulation_core::mips::memory::Memory;
 use crate::emulation_core::register::{RegisterType, Registers};
 use crate::emulation_core::riscv::datapath::{RiscDatapathState, RiscStage};
-use crate::emulation_core::riscv::registers::{RiscGpRegisterType, RiscGpRegisters};
+use crate::emulation_core::riscv::registers::{
+    RiscFpRegisters, RiscGpRegisterType, RiscGpRegisters,
+};
 use crate::emulation_core::stack::Stack;
 use gloo_console::log;
 use std::rc::Rc;
@@ -40,6 +42,7 @@ pub struct MipsCoreState {
 pub struct RiscCoreState {
     pub state: RiscDatapathState,
     pub registers: RiscGpRegisters,
+    pub coprocessor_registers: RiscFpRegisters,
     pub memory: Memory,
     pub current_stage: RiscStage,
     pub stack: Stack,
@@ -151,6 +154,12 @@ impl Reducible for DatapathReducer {
                         stack,
                         ..self.riscv.clone()
                     },
+                    RiscStateUpdate::UpdateCoprocessorRegisters(coprocessor_registers) => {
+                        RiscCoreState {
+                            coprocessor_registers,
+                            ..self.riscv.clone()
+                        }
+                    }
                 },
                 ..(*self).clone()
             },
@@ -169,7 +178,7 @@ impl DatapathReducer {
     pub fn get_sp(&self) -> u64 {
         match self.current_architecture {
             MIPS => self.mips.registers[GpRegisterType::Sp],
-            RISCV => self.riscv.registers[RiscGpRegisterType::X1],
+            RISCV => self.riscv.registers[RiscGpRegisterType::X2],
         }
     }
 
@@ -180,13 +189,27 @@ impl DatapathReducer {
         }
     }
 
+    pub fn get_dyn_fp_registers(&self) -> Vec<(Rc<dyn RegisterType>, u64)> {
+        match self.current_architecture {
+            MIPS => self.mips.coprocessor_registers.get_dyn_register_list(),
+            RISCV => self.riscv.coprocessor_registers.get_dyn_register_list(),
+        }
+    }
+
     pub fn get_memory(&self) -> &Memory {
         match self.current_architecture {
             MIPS => &self.mips.memory,
             RISCV => &self.riscv.memory,
         }
     }
 
+    pub fn get_current_stage(&self) -> String {
+        match self.current_architecture {
+            MIPS => self.mips.current_stage.into(),
+            RISCV => self.riscv.current_stage.into(),
+        }
+    }
+
     pub fn get_stack(&self) -> &Stack {
         match self.current_architecture {
             MIPS => &self.mips.stack,

src/agent/messages.rs

@@ -4,7 +4,7 @@ use crate::emulation_core::mips::fp_registers::FpRegisters;
 use crate::emulation_core::mips::gp_registers::GpRegisters;
 use crate::emulation_core::mips::memory::Memory;
 use crate::emulation_core::riscv::datapath::{RiscDatapathState, RiscStage};
-use crate::emulation_core::riscv::registers::RiscGpRegisters;
+use crate::emulation_core::riscv::registers::{RiscFpRegisters, RiscGpRegisters};
 use crate::emulation_core::stack::Stack;
 use crate::emulation_core::{architectures::AvailableDatapaths, mips::datapath::Stage};
 use serde::{Deserialize, Serialize};
@@ -44,6 +44,7 @@ pub enum MipsStateUpdate {
 pub enum RiscStateUpdate {
     UpdateState(RiscDatapathState),
     UpdateRegisters(RiscGpRegisters),
+    UpdateCoprocessorRegisters(RiscFpRegisters),
     UpdateMemory(Memory),
     UpdateStage(RiscStage),
     UpdateStack(Stack),

src/bin/main.rs

@@ -35,14 +35,13 @@ use web_sys::HtmlInputElement;
 use yew::prelude::*;
 use yew::{html, Html, Properties};
 
-use swim::emulation_core::register::Registers;
 use swim::emulation_core::riscv::datapath::RiscStage;
 use yew_agent::Spawnable;
 
 // To load in the Fibonacci example, uncomment the CONTENT and fib_model lines
 // and comment the code, language, and text_model lines. IMPORTANT:
 // rename fib_model to text_model to have it work.
-const CONTENT: &str = include_str!("../../static/assembly_examples/fibonacci.asm");
+const CONTENT: &str = include_str!("../../static/assembly_examples/riscv_fib.asm");
 
 #[derive(Properties, Clone, PartialEq)]
 struct AppProps {
@@ -238,7 +237,10 @@ fn app(props: &AppProps) -> Html {
 
                 let list_of_line_numbers = program_info.address_to_line_number;
                 let index = datapath_state.get_pc() as usize / 4;
-                editor_curr_line.set(*list_of_line_numbers.get(index).unwrap_or(&0) as f64 + 1.0); // add one to account for the editor's line numbers
+                editor_curr_line.set(match list_of_line_numbers.get(index) {
+                    Some(val) => (val + 1) as f64,
+                    None => 0f64,
+                });
                 memory_curr_instr.set(datapath_state.get_pc());
 
                 // Execute instruction
@@ -297,8 +299,10 @@ fn app(props: &AppProps) -> Html {
 
                     let list_of_line_numbers = program_info.address_to_line_number;
                     let index = datapath_state.get_pc() as usize / 4;
-                    editor_curr_line
-                        .set(*list_of_line_numbers.get(index).unwrap_or(&0) as f64 + 1.0);
+                    editor_curr_line.set(match list_of_line_numbers.get(index) {
+                        Some(val) => (val + 1) as f64,
+                        None => 0f64,
+                    });
                     memory_curr_instr.set(datapath_state.get_pc());
                     communicator.execute_stage();
                 } else {
@@ -570,7 +574,7 @@ fn app(props: &AppProps) -> Html {
     };
 
     html! {
-        <>
+        <div class="overflow-hidden">
             // button tied to the input file element, which is hidden to be more clean
             <input type="file" class="hidden" id="file_input" accept=".txt,.asm,.mips" onchange={file_picked_callback} />
             <div class="flex flex-row flex-no-wrap h-screen p-2 gap-2">
@@ -667,9 +671,9 @@ fn app(props: &AppProps) -> Html {
                 </div>
 
                 // Right column
-                <Regview gp={datapath_state.get_dyn_gp_registers()} fp={datapath_state.mips.coprocessor_registers.get_dyn_register_list()} pc_limit={*pc_limit} communicator={props.communicator}/>
+                <Regview gp={datapath_state.get_dyn_gp_registers()} fp={datapath_state.get_dyn_fp_registers()} pc_limit={*pc_limit} communicator={props.communicator}/>
             </div>
-        </>
+        </div>
     }
 }
 

src/emulation_core/riscv.rs

@@ -3,6 +3,7 @@
 
 pub mod constants;
 pub mod control_signals;
+pub mod coprocessor;
 pub mod datapath;
 pub mod datapath_signals;
 pub mod instruction;

src/emulation_core/riscv/constants.rs

@@ -44,6 +44,7 @@ pub const FUNCT_SOP37: u8 = 0b011111;
 /// Used for R-type instructions.
 pub const OPCODE_OP: u8 = 0b0110011;
 pub const OPCODE_OP_32: u8 = 0b0111011;
+pub const OPCODE_OP_FP: u8 = 0b1010011;
 
 /// Used for I-type instructions.
 pub const OPCODE_IMM: u8 = 0b0010011;
@@ -52,11 +53,13 @@ pub const OPCODE_IMM_32: u8 = 0b0011011;
 pub const OPCODE_JALR: u8 = 0b1100111;
 // LOAD
 pub const OPCODE_LOAD: u8 = 0b0000011;
+pub const OPCODE_LOAD_FP: u8 = 0b0000111;
 // SYSTEM
 pub const OPCODE_SYSTEM: u8 = 0b1110011;
 
 /// Used for S-type instructions.
 pub const OPCODE_STORE: u8 = 0b0100011;
+pub const OPCODE_STORE_FP: u8 = 0b0100111;
 
 /// Used for B-type instructions.
 pub const OPCODE_BRANCH: u8 = 0b1100011;
@@ -70,6 +73,19 @@ pub const OPCODE_AUIPC: u8 = 0b0010111;
 /// Used for J-type instructions.
 pub const OPCODE_JAL: u8 = 0b1101111;
 
+/// Used for R4-type instructions.
+// FMADD.S
+pub const OPCODE_MADD: u8 = 0b1000011;
+// FMSUB.S
+pub const OPCODE_MSUB: u8 = 0b1000111;
+// FNMSUB.S
+pub const OPCODE_NMSUB: u8 = 0b1001011;
+// FNMADD.S
+pub const OPCODE_NMADD: u8 = 0b1001111;
+
+/// Not a Number
+pub const RISC_NAN: u32 = 0x7fc00000;
+
 // "ENC" is short for encoding. There is no formal name for this field
 // in the MIPS64 specification, other than the "shamt"/"sa" field that it
 // replaces, so this was chosen as the mnemonic for this project.