Riscv-fpu #368
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Riscv-fpu #368
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Moving on to FPU control signals.
the entire way through.
Subtraction, Multiplication, and Division. Fixed errors. SWIM_v2 once again compiles and works. FPU support still rudimentary, will continue to add instructions until the end of Thursday.
Remaining FP Operations: * R4 Types * Conversion + Move * Comparisons * Classify * 64-Bits
to Integer Registers.
to FP Registers.
bits, compliant with RV64F (In spite of its confusing name).
Notable FPU branching logic which doesn't exist in RISC-V.
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Implemented FPU and all RV32F and 64F instructions.