- The Silicon Electronic Photonics Integrated Circuits (SiEPIC) fabrication program, SiEPICfab, presents the open electron beam lithography (EBL) fabrication process, where former and current students of SiEPIC workshops and courses can submit their design for manufacturing and testing.
- More details about openEBL.
- Submission deadline: extended to November 4, 2024.
- SOI wafer, 400 nm silicon nitride (see the layer builder file SiN.lbr for process bias and sidewall angle information), and Applied Nanotools webpage
- Baseline process:
- Single full etch, using a negative resist (HSQ)
- Oxide cladding
- Edge coupling
- Facet-attached micro-lenses and vertical emitters, by Dream Photonics
- Process Design Kit: SiEPIC-EBeam-PDK
- Design for Test rules
| Name | Layer/datatype | Description |
|---|---|---|
| SiN | 4/0 | [Fabricated] Layer to draw silicon nitride geometries |
| Floorplan | 99/0 | [Virtual] Marks the layout design area |
| Text | 10/0 | [Virtual] Text labels for automated measurements |
| DevRec | 68/0 | [Virtual] Device recognition layer for component connectivity, netlist extraction, and verification |
| PinRec | 1/10 | [Virtual] Port/pins recognition layer for component connectivity, netlist extraction, and verification |
| Waveguide | 1/99 | [Virtual] Guiding shape for waveguide, used for length calculation |
| SEM | 200/0 | [Virtual] Requests for SEM images. Rectangles in a 4:3 aspect ratio |
The submission involves several steps. First, you need to create your design(s) using the process design kit (PDK) for this specific fabrication run. Then you need to create a Fork of this repository, commit your design(s), ensure that it passes the checks, and create a pull request. Once your pull request is approved, your design(s) will be merged into the layout for fabrication. You should verify that your design is correctly merged. Once the designs are fabricated, they will be tested, and the measurement results will be posted in this repository.
- Design Verification: the design must be error-free, namely passing
- the DRC manufacturing checks, and
- the Functional Layout Check ("V" in KLayout SiEPIC-Tools)
- Design tools and process design kit (SiEPIC-EBeam-PDK, KLayout implementation) installation instructions.
- Create your design using Python (example Jupyter notebook, example Python file) or using the Graphical Interface in KLayout
- Watch this video for a demonstration
- Create an account on GitHub
- Fork a copy of this GitHub repository into your own account: Create a new fork.
- Turn on the GitHub Actions on your forked repository: Actions (In your repository's page on GitHub, click on Actions in the top-menu bar, and Enable the workflows).
- [Optional] Install GitHub Desktop (or git) on your computer, and Clone a local copy: Open with GitHub Desktop
- Create your design, and ensure that the filename contains your edX.org (or GitHub username if the edX one is a random string that does not contain your name), and be formatted according to the course/workshop as follows:
- EBeam_username.oas: for the edX Phot1x silicon photonics design course
- ELEC413_username.oas: for the UBC ELEC 413 course
- SiEPIC_Passives_username.oas: for the CMC SiEPIC Passives silicon photonics workshop
- openEBL_username.gds: for past participants in the above courses, conference short courses
- For example: EBeam_LukasChrostowski_rings.oas
- Ensure that your fork is up to date with the main SiEPIC repository. Click "Sync fork"
- Upload your design(s) into the "submissions" folder, as a binary file, namely a .gds (GDSII format) or .oas (OASIS format) file.
- This can be done via the GitHub web page, by navigating to the submissions folder, then clicking on Add file, and Upload files.
- Click Commit changes, and wait for the verification (via GitHub actions) to complete. This will appear as a green checkmark or red X next to your commit on GitHub.
- If there are errors, please review and correct the errors.
- Please run your verification locally (press V in KLayout), or download the output .lydrb verification file from GitHub and open in KLayout.
- Look for errors -- "All checks have failed"
- Click on Details
- In the main, window expand the "Run layout verification"; see if there is a text description of the problem
- Look for the Artifact file; download it and open it in KLayout
- After fixing the errors, you should have a green check mark as follows:
- Alternatively upload your Python file, which will be compiled by a GitHub Action.
- For KLayout designs, use the "submissions/KLayout Python" folder, namely a .py (Python format) file. e.g., EBeam_LukasChrostowski_MZI.py. The Python file should save a gds or oas file into the parent "submissions" folder. The Python script needs to be executable in non-GUI mode, namely using "import klayout SiEPIC SiEPIC-EBeam-PDK"
- Create a Pull Request -- this will notify the team of your contribution, which we can aggregate into the main design file
- Return to the main repository, and ensure that your design is correctly merged. Download the Latest Merge file, below.
- We perform IP replacement on several cells (grating couplers). We call these cells Black Box (BB), and you can identify them by _BB in the cell name, or the presence of the Blackbox layer 998/0 in the cell.
- You must not change the name of the cell, the contents, nor cell origins. Otherwise, the replacement will not work correctly.
The verification and merging is performed using GitHub actions. The repository implements the following:
- Running the Python files in the "submissions/KLayout Python" folder, to generate the designs
- Performing Manufacturing DRC verification on the designs in the "submissions" folder, and outputing the errors as an Artifact
- Performing Functional verification on the designs in the "submissions" folder, and outputing the errors as an Artifact
- Merging the designs from the "submissions" folder, and outputing merged layout as an Artifact in the main repository
https://github.com/SiEPIC/openEBL-2024-10-SiN/actions/runs/11698397925/artifacts/2150640087