-
Notifications
You must be signed in to change notification settings - Fork 102
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Final Chip 1 Layout #9
base: main
Are you sure you want to change the base?
Conversation
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
Thank you for your pull request! 👋 |
still need to fix verification errors.
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
Thank you for your pull request! 👋 |
Can you rename your files per the naming convension? |
You have two files. Can you please delete the one that should not be fabricated? |
Yes will do soon! I apologize I'm behind on perfecting my Chip 1 to be
honest and I know I still have verification errors on my design that need
to be fixed. I'm aiming to be completely done Chip 1 and reupload my file
with the correct naming conventions by tonight. Thank you!
…On Mon, Feb 3, 2025 at 11:02 PM Lukas Chrostowski ***@***.***> wrote:
You have two files. Can you please delete the one that should not be
fabricated?
—
Reply to this email directly, view it on GitHub
<#9 (comment)>,
or unsubscribe
<https://github.com/notifications/unsubscribe-auth/AJDFSURVGRWRZJHETUKA5GT2OBQY5AVCNFSM6AAAAABWDZVZGWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDMMZTGA2DINRYGI>
.
You are receiving this because you authored the thread.Message ID:
***@***.***>
|
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
Thank you for your pull request! 👋 |
1 similar comment
Thank you for your pull request! 👋 |
Ebeam file for fabrication
Thank you for your pull request! 👋 |
Hi Prof Lukas, as we discussed after class (error with mismatched pins due to different width waveguides being connected), I've added the two files you wanted to see to check the error. After restarting Klayout I got the same error. |
Thank you for your pull request! 👋 |
1 similar comment
Thank you for your pull request! 👋 |
Thank you for your pull request! 👋 |
Thank you! I've fixed all the verification errors now and have 4 variations in my design to account for differences in the width of the waveguide due to manufacturing tolerances. |
No description provided.