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Releases: SiLab-Bonn/basil

v3.2.0

25 Jun 19:48
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  • Only Python >= 3.7 support
  • Use GHA for CI
  • Add split data bus module #145 #151 #153
  • Add basic Verilotor support #146 #148 #149 #150
  • Fix bug and compatibility issues of SHT85 driver
  • Use NBA for the clock divider #156
  • Signature support #158
  • Update and improve seq_rec, seq_gen and jtag_master modules #161 #162 (it will not work with ISE)
  • Update simulation framework #163

v3.1.0

02 Dec 12:22
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This is the last version with Python 2.7 support

  • many fixes and cleanups and improvements
  • support for si570 chip
  • new JTAG module

v3.0.1

17 Sep 20:58
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Enhancing Python 3.7 compatibility. Python 2.7 compatibility still maintained.

  • adding support for Julabo F32-HD chiller
  • adding support for ISO-DEBYEFLEX3003 X-Ray machine
  • code cleanup and PEP8
  • improving support for cocotb 1.0 and later

v3.0.0

08 Feb 14:33
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Providing Python 3.7 compatibility.

  • added BDAQ53 example
  • moved firmware folder to basil/firmware to be contained in package
  • fixed cocotb issues
  • fixed improper clear of SiTCP buffer

v2.4.13

03 Nov 19:36
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  • increased SiTCP connection timeout to 5s
  • sharing fast trigger between TDC instances
  • fixed get_voltage() in NTCRegister
  • support external timestamp in TLU FSM
  • fixed control registers in timestamp_div_core.v and timestamp_core.v
  • added trip reset for TTL QL series
  • improved import error handling for external modules
  • fixed length of TLU_ENABLED/TRIGGER_ENABLED signal in TLU FSM

v2.4.12

16 May 09:55
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  • adding high resolution time stamp module
  • adding software trigger (TLU/TRIGGER FSM)
  • adding reset signal for the timestamp (TLU/TRIGGER FSM)
  • increasing trigger delay parameter from 4 bits to 8 bits (TLU/TRIGGER FSM)
  • improvements and bug fixing of UDP to BUS (RBCP) interface (SiTCP TL)
  • adding TCP to BUS module (as a replacement for RBCP)
  • implement close() for SiTCP TL
  • adding no_calibration parameter to FEI4QuadModuleAdapterCard
  • adding TCP and UDP speed test (firmware and example)
  • lots of code cleanup

v2.4.11

15 Feb 14:50
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  • supporting PLL chip (CY22150) on the MIO3/MMC3 board
  • adding module-level logging
  • fixing DUT.close() behavior
  • properly close SiTCP connection and stop thread
  • cleanup of setup.py

v2.4.10

18 Dec 09:05
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REG: fixing parameter

v2.4.9

15 Dec 14:26
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ENH: FORCE_SDA_READBACK_ZERO -> IGNORE_ACK
ENH: adding more Tektronix scope commands

v2.4.6

26 Jul 13:33
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MAINT: adding examples
MAINT: fixing Cocotb issues
ENH: Sensirion stability improvements
ENH: adding variable size of trigger/veto input to TLU/trigger FSM
ENH: adding enabled signal to FEI4 Rx