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Pull requests: SpinalHDL/SpinalHDL

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Pull requests list

[RegIf] Fix the "BusInterface" and add a new function to change the default error state
#1632 opened Dec 24, 2024 by HaroldZ32 Loading…
1 of 2 tasks
Interface-related SystemVerilog Code Emission Enhancements
#1631 opened Dec 23, 2024 by fl4shk • Draft
2 tasks
1
"add one more apply method for isPow2"
#1630 opened Dec 20, 2024 by facebreeze Loading…
Fix simulation failure with Verilator v5.x on Windows
#1618 opened Dec 10, 2024 by du33169 Loading…
2 tasks
1
7
lib/bus/bmb/BmbDecoder: Fix missing wirings when invalidation is enabled
#1608 opened Dec 3, 2024 by cherrypiejam Loading…
2 tasks
4
Fix incorrect interconnect addressWidth generation
#1607 opened Dec 3, 2024 by cherrypiejam Loading…
2 tasks
8
Make 2.11 & 2.13 CI test always.
#1589 opened Nov 5, 2024 by Readon • Draft
1 task
2
fix test initial value problem for Dfi Controller.
#1581 opened Oct 29, 2024 by Readon Loading…
2 tasks
1
Fix FSM bug
#1529 opened Sep 7, 2024 by thajohns Loading…
1 task done
1
4
Add mill template link to readme
#1505 opened Aug 13, 2024 by mrcmry Loading…
2
Add SamplerCC pushCd(reg) -> popCd(BufferCC)
#1500 opened Aug 5, 2024 by Dolu1990 Loading…
set rst name for default clock domain by ClockDomainConfig
#1484 opened Jul 17, 2024 by yportne13 Loading…
1
RFC: Add blackboxing for simple 1-port synchronous ROMs
#1475 opened Jul 11, 2024 by bunnie Loading…
2 tasks
20
ACE & ACE-Lite support
#1450 opened Jun 12, 2024 by KireinaHoro • Draft
3 of 8 tasks
5
Bugfix/wb pipelined
#1375 opened Mar 26, 2024 by jdavidberger Loading…
1
71
Ability to remap address for BusSlaveFactory
#1354 opened Mar 13, 2024 by KireinaHoro • Draft
2 tasks
14
Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now
#1315 opened Feb 19, 2024 by janschiefer Loading…
1
TaggedUnion implementation
#1241 opened Nov 10, 2023 by ronan-lashermes Loading…
2 tasks
35
[feature] FuseSocGeneratorBuilder provide a easy way to use fusesoc
#1232 opened Nov 2, 2023 by chenbo-again Loading…
27
feat: add loadHex function for SparseMemory
#1015 opened Jan 12, 2023 by hanm2019 Loading…
1 of 2 tasks
1
6
Add ethernet udp tx/rx module feature ✨ Feature idea with clear API defined wontfix The issue would not be fixed
#1010 opened Jan 10, 2023 by jjyy-Huang Loading…
1 of 7 tasks
16
feature: add new optional reset signal to StreamWidthAdapter and StreamFragmentWidthAdapter
#1008 opened Jan 8, 2023 by jonnykl Loading…
2 tasks
6
Move tests
#1001 opened Dec 18, 2022 by numero-744 • Draft
4 tasks
1
25
feat: SpinalTestBench
#968 opened Nov 19, 2022 by numero-744 Loading…
2 tasks done
v1.8.1
@numero-744
100
feat: protocol simulation API; implemented for AHB
#879 opened Oct 3, 2022 by numero-744 • Draft
1
31
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