This branch is 1 commit behind vinamarora8/Radix-2-FFT:master.

Name	Name	Last commit message	Last commit date
Latest commit vinamarora8 Adds main.ucf Mar 28, 2017 c6a7483 · Mar 28, 2017 History 77 Commits
.gitignore	.gitignore	Changes .gitignore	Mar 26, 2017
D_latch.v	D_latch.v	Adds D_latch.v	Mar 8, 2017
README.md	README.md	Adds TODO to README.md	Mar 7, 2017
T_flipflop.v	T_flipflop.v	Improves logic of T_flipflop.v	Mar 26, 2017
address_gen_unit.v	address_gen_unit.v	Modifies AGU a little. Nothing major	Mar 28, 2017
butterfly_unit.v	butterfly_unit.v	Makes changes to butterfly_unit.v, in particular, adds the 7fff ~ 1.0…	Mar 27, 2017
clock_delay.v	clock_delay.v	Adds sync clear function to clock_delay.v	Mar 14, 2017
counter_3bm5.v	counter_3bm5.v	Fixes cout in counter_3bm5.v	Mar 11, 2017
counter_4b.v	counter_4b.v	Renames Counters to match standard (all low)	Mar 7, 2017
counter_5b.v	counter_5b.v	Adds counter_5b.v	Mar 28, 2017
fft.v	fft.v	Incorporates external mem access in fft.v	Mar 28, 2017
incrementer.v	incrementer.v	Fixes bugs in incrementer.v. Tested. Works perfectly	Mar 8, 2017
input_mem_initialization.coe	input_mem_initialization.coe	Modifies input_mem_init.v to incorporate address bit-flip during write	Mar 28, 2017
main.ucf	main.ucf	Adds main.ucf	Mar 28, 2017
main.v	main.v	Changes main.v. Adds extra information I/O signals	Mar 28, 2017
mem_check.v	mem_check.v	Modifies mem_check.v. Fixes a logic error	Mar 28, 2017
memory_2_bank.v	memory_2_bank.v	Modifies memory_2_bank.v, some connections reversed	Mar 28, 2017
result_check_mem_initializtion.coe	result_check_mem_initializtion.coe	Updates result_check_mem_initialization.coe	Mar 28, 2017
right_shift.v	right_shift.v	Changes right_shift.v to correct a semantic error	Mar 15, 2017
rotate_left_5b.v	rotate_left_5b.v	Declares rotate_left_5b.v as tested. Works perfectly	Mar 8, 2017
sync_SR_latch.v	sync_SR_latch.v	Adds 'endmodule' to sync_sr_latch	Mar 8, 2017
twiddle_factor_ROM.v	twiddle_factor_ROM.v	Adds twiddle_factor_ROM.v, necessary for ROM's xco file	Mar 26, 2017
twiddle_factor_ROM_initialization.coe	twiddle_factor_ROM_initialization.coe	Adds twiddle_factor_ROM_initialization.coe	Mar 15, 2017

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Radix-2 Fast Fourier Transform for FPGA

Coded in Verilog

TODO:

Address Generating Unit
Butterfly Unit
Twiddle Factor ROM
BRAMs
Communication with a computer

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Radix-2 Fast Fourier Transform for FPGA

TODO:

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Radix-2 Fast Fourier Transform for FPGA

TODO:

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