synth: Run clockgate for automatic ICG insertion
#2657
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Signed-off-by: Martin Povišer <[email protected]>
povik
reviewed
Jan 6, 2025
| @@ -65,8 +65,10 @@ foreach cell $::env(DONT_USE_CELLS) { | |||
| # Technology mapping of flip-flops | |||
| # dfflibmap only supports one liberty file | |||
| if {[env_var_exists_and_non_empty DFF_LIB_FILE]} { | |||
| clockgate -liberty $::env(DFF_LIB_FILE) -min_net_size 8 {*}$dfflibmap_args | |||
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The min_net_size value could be a flow parameter, do you want me to make it one? MIN_CLOCK_GATE_FF_GROUP ?
|
The code looks fine but I'm confused where there are so many failures. I don't think gcd has any clock gaters yet it failed. |
I will take a look but I expect they get inferred because there's a shared enable on the flops |
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Yosys 0.48 has gained
clockgate -libertycommand for rudimentary clock gate insertion triggered when a group of flip-flops share the same enable condition. Start using this command in the ORFS flow.Cc @widlarizer