Add openFPGALoader section

main.tex

@@ -65,6 +65,7 @@
 \input{sections/run}
 \input{sections/limitations}
 \input{sections/ci}
+\input{sections/ofl}
 
 \clearpage % If you want the references in a separate page
 \bibliography{bibliography}

sections/ci.tex

@@ -57,20 +57,19 @@ \section{Implementation the workflow through CI}
 \label{cod:7}
 \end{code}
 
-\vspace{5mm}
+\vspace{3mm}
 
 \noindent Lines 10-11 and 30-31 set the environment variable.
 
-\vspace{5mm}
+\vspace{3mm}
 
 \noindent Lines 18 and 38 set the container.
 
-\vspace{5mm}
+\vspace{3mm}
 
 \noindent Lines 20 and 40 run the script through the container.
 
+\vspace{3mm}
 
-\vspace{5mm}
-
-\noindent Lines 22-23-24-25-26 and 42-43-44-45-46 upload the generated bitstream as an artifact.
+\noindent Lines 22-23-24-25-26 and 42-43-44-45-46 upload the bitstream as an artifact.
 

sections/introduction.tex

@@ -17,19 +17,19 @@ \subsection{Container: ghcr.io/unike267/containers/impl-arty:latest}
     \item Project X-Ray \cite{gh:prjxray}
 \end{itemize}
 
-\noindent In this context the workflow to generate a bitstream from VHDL code is as follows:
+\noindent In this context, the workflow to generate a bitstream from VHDL code is as follows:
 
 \begin{itemize}
     \item First, GHDL tool compiles the VHDL code of the design.
-    \item Second, ghdl-yosys-plugin import the synthesized code to Yosys. 
+    \item Second, ghdl-yosys-plugin imports the synthesized code to Yosys. 
 \footnote{This plugin is necessary because Yosys, by default, is designed to synthesize verilog.} 
 \footnote{ghdl-yosys-plugin is a thin layer that converts the internal representation of \mintinline[breaklines]{bash}{--synth} to Yosys’ C API.}
     \item Then, Yosys synthesis suite performs the synthesis/mapping for Xilinx 7-Series FPGAs.
     \item Third, Nextpnr-Xilinx tool performs the P\&R specifically for the Arty A7 35T or 100T FPGA.
     \item Finally, Project X-Ray generates the bitstream.
 \end{itemize}
 
-\noindent In addition to this, openFPGALoader \cite{gh:openFPGALoader} is used to load the output bitstream into the Arty FPGAs.
+\noindent In addition to this, openFPGALoader \cite{gh:openFPGALoader} is used to load the output bitstream into the Arty FPGAs, see section \ref{ofl}.
 
 \vspace{5mm}
 

sections/ofl.tex

@@ -0,0 +1,15 @@
+\section{openFPGALoader to load the output bitstream to an Arty FPGA.}
+
+\label{ofl}
+
+To load a bitstream to an Arty board (both A7 35t and A7 100t) through openFPGALoader use this command: 
+
+\begin{code}
+\begin{minted}[frame=lines,framesep=2mm,baselinestretch=1.2,fontsize=\footnotesize,breaklines]{bash}
+openFPGALoader --board arty name_of_bitstream.bit
+\end{minted}
+\caption{Command to load a bitstream to an Arty board through openFPGALoader.}
+\label{cod:7}
+\end{code}
+
+