[skip ci] Updates

_sources/developer/arch/supported/aarch64.rst.txt

@@ -211,9 +211,15 @@ Loads and stores
 
 In addition to an execution behaviour, memory instructions also require a new entry in the address generation behaviour table found in ``src/lib/arch/aarch64/Instruction_address.cc``. These entries are responsible for describing the method used to generate the addresses that these instructions will read from or write to.
 
-Address generation is expected to generate one or more instances of ``MemoryAddressTarget``, containing an address and the number of bytes to access. The same variables described above (``operands``, ``metadata``) are available to use to generate these addresses.
+Address generation is expected to generate one or more instances of ``MemoryAccessTarget``, containing an address and the number of bytes to access. The same variables described above (``operands``, ``metadata``) are available to use to generate these addresses.
 
-Once the addresses have been generated, they should be supplied in a vector to the ``setMemoryAddresses`` helper function.
+Once the addresses have been generated, they should be supplied in a vector to the ``setMemoryAddresses`` helper function. 
+
+For loads, data can be read from the ``memoryData`` vector in ``Instruction_execute.cc``, with each index holding a ``RegisterValue`` for a corresponding ``MemoryAccessTarget``. For stores, a ``RegisterValue`` must be placed in each index of the ``memoryData`` vector, again one per ``MemoryAccessTarget`` generated.
+
+To best match modelled hardware, contiguous Load and Store instructions use one ``MemoryAccessTarget`` per destination/source register. For NEON instructions this should always be the case, including interleaved multi-structure loads / stores.
+
+Concerning SVE & SME loads and stores, an effort should be made to merge contiguous active elements into as few ``MemoryAccessTarget``'s as possible by evaluating the predicate information (if applicable). Helper functions ``sve_merge_store_data`` and ``generatePredicatedContiguousAddressBlocks`` can be used to support this.
 
 
 Instruction aliases

_sources/index.rst.txt

@@ -70,6 +70,7 @@ SimEng was first presented by `Professor Simon McIntosh-Smith <http://uob-hpc.gi
 
 Additionally, other works concerning SimEng and its use can be found below:
 
+- ModSim 2023 - :download:`Leveraging Arm's Scalable Matrix Extension to Accelerate Matrix Multiplication Kernels <assets/modsim23_poster.pdf>`
 - ModSim 2022 - :download:`A design space exploration for optimal vector unit composition <assets/modsim22_poster.pdf>`
 - :download:`Modelling Advanced Arm-based CPUs with SimEng <assets/simeng_arm_cpus.pdf>`
 

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developer/arch/supported/aarch64.html

@@ -420,8 +420,11 @@ <h3><a class="toc-backref" href="#id13">Zero registers</a><a class="headerlink"
 <div class="section" id="loads-and-stores">
 <h3><a class="toc-backref" href="#id14">Loads and stores</a><a class="headerlink" href="#loads-and-stores" title="Permalink to this headline">¶</a></h3>
 <p>In addition to an execution behaviour, memory instructions also require a new entry in the address generation behaviour table found in <code class="docutils literal"><span class="pre">src/lib/arch/aarch64/Instruction_address.cc</span></code>. These entries are responsible for describing the method used to generate the addresses that these instructions will read from or write to.</p>
-<p>Address generation is expected to generate one or more instances of <code class="docutils literal"><span class="pre">MemoryAddressTarget</span></code>, containing an address and the number of bytes to access. The same variables described above (<code class="docutils literal"><span class="pre">operands</span></code>, <code class="docutils literal"><span class="pre">metadata</span></code>) are available to use to generate these addresses.</p>
+<p>Address generation is expected to generate one or more instances of <code class="docutils literal"><span class="pre">MemoryAccessTarget</span></code>, containing an address and the number of bytes to access. The same variables described above (<code class="docutils literal"><span class="pre">operands</span></code>, <code class="docutils literal"><span class="pre">metadata</span></code>) are available to use to generate these addresses.</p>
 <p>Once the addresses have been generated, they should be supplied in a vector to the <code class="docutils literal"><span class="pre">setMemoryAddresses</span></code> helper function.</p>
+<p>For loads, data can be read from the <code class="docutils literal"><span class="pre">memoryData</span></code> vector in <code class="docutils literal"><span class="pre">Instruction_execute.cc</span></code>, with each index holding a <code class="docutils literal"><span class="pre">RegisterValue</span></code> for a corresponding <code class="docutils literal"><span class="pre">MemoryAccessTarget</span></code>. For stores, a <code class="docutils literal"><span class="pre">RegisterValue</span></code> must be placed in each index of the <code class="docutils literal"><span class="pre">memoryData</span></code> vector, again one per <code class="docutils literal"><span class="pre">MemoryAccessTarget</span></code> generated.</p>
+<p>To best match modelled hardware, contiguous Load and Store instructions use one <code class="docutils literal"><span class="pre">MemoryAccessTarget</span></code> per destination/source register. For NEON instructions this should always be the case, including interleaved multi-structure loads / stores.</p>
+<p>Concerning SVE &amp; SME loads and stores, an effort should be made to merge contiguous active elements into as few <code class="docutils literal"><span class="pre">MemoryAccessTarget</span></code>’s as possible by evaluating the predicate information (if applicable). Helper functions <code class="docutils literal"><span class="pre">sve_merge_store_data</span></code> and <code class="docutils literal"><span class="pre">generatePredicatedContiguousAddressBlocks</span></code> can be used to support this.</p>
 </div>
 <div class="section" id="instruction-aliases">
 <h3><a class="toc-backref" href="#id15">Instruction aliases</a><a class="headerlink" href="#instruction-aliases" title="Permalink to this headline">¶</a></h3>

index.html

@@ -217,6 +217,7 @@ <h2>Talks and presentations<a class="headerlink" href="#talks-and-presentations"
 </ul>
 <p>Additionally, other works concerning SimEng and its use can be found below:</p>
 <ul class="simple">
+<li>ModSim 2023 - <a class="reference download internal" href="_downloads/modsim23_poster.pdf" download=""><code class="xref download docutils literal"><span class="pre">Leveraging</span> <span class="pre">Arm's</span> <span class="pre">Scalable</span> <span class="pre">Matrix</span> <span class="pre">Extension</span> <span class="pre">to</span> <span class="pre">Accelerate</span> <span class="pre">Matrix</span> <span class="pre">Multiplication</span> <span class="pre">Kernels</span></code></a></li>
 <li>ModSim 2022 - <a class="reference download internal" href="_downloads/modsim22_poster.pdf" download=""><code class="xref download docutils literal"><span class="pre">A</span> <span class="pre">design</span> <span class="pre">space</span> <span class="pre">exploration</span> <span class="pre">for</span> <span class="pre">optimal</span> <span class="pre">vector</span> <span class="pre">unit</span> <span class="pre">composition</span></code></a></li>
 <li><a class="reference download internal" href="_downloads/simeng_arm_cpus.pdf" download=""><code class="xref download docutils literal"><span class="pre">Modelling</span> <span class="pre">Advanced</span> <span class="pre">Arm-based</span> <span class="pre">CPUs</span> <span class="pre">with</span> <span class="pre">SimEng</span></code></a></li>
 </ul>