Fix array vs. element logical operator

VHDL-LS · Feb 5, 2023 · c982983 · c982983
1 parent 2597388
commit c982983
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/vhdl_lang/src/analysis/standard.rs b/vhdl_lang/src/analysis/standard.rs
@@ -909,7 +909,7 @@ impl<'a> AnalyzeContext<'a> {
                     // A op S -> A
                     self.binary(op, atyp, atyp, styp, atyp),
                     // S op A -> A
-                    self.binary(op, atyp, atyp, atyp, styp),
+                    self.binary(op, atyp, styp, atyp, atyp),
                 ]
                 .into_iter()
             });