fpga/ips: add invalidate method to AxisCache and whitelist the IP in …

…hwdef-parse.py Signed-off-by: Niklas Eiling <[email protected]>
VILLASframework · Oct 31, 2024 · 5876bb1 · 5876bb1
1 parent f8401cf
commit 5876bb1
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Showing 2 changed files with 11 additions and 1 deletion.
diff --git a/fpga/lib/ips/axis_cache.cpp b/fpga/lib/ips/axis_cache.cpp
@@ -17,7 +17,10 @@ using namespace villas::fpga::ip;
 
 AxisCache::AxisCache() : Node() {}
 
-bool AxisCache::init() { return true; }
+bool AxisCache::init() {
+  invalidate();
+  return true;
+}
 
 bool AxisCache::check() {
 
@@ -47,6 +50,11 @@ bool AxisCache::check() {
   return true;
 }
 
+void AxisCache::invalidate() {
+  setRegister(0, 1U << 31);
+  logger->info("invalidated AXIS cache.");
+}
+
 void AxisCache::setRegister(size_t reg, uint32_t value) {
   if (reg >= registerNum) {
     logger->error("Register index out of range: {}/{}", reg, registerNum);

diff --git a/tools/hwdef-parse.py b/tools/hwdef-parse.py
@@ -50,6 +50,7 @@
     ["xilinx.com", "module_ref", "dinoif_dac"],
     ["xilinx.com", "module_ref", "axi_pcie_intc"],
     ["xilinx.com", "module_ref", "registerif"],
+    ["xilinx.com", "module_ref", "axi_read_cache"],
     ["xilinx.com", "hls", "rtds2gpu"],
     ["xilinx.com", "hls", "mem"],
     ["acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc"],
@@ -69,6 +70,7 @@
     ["xilinx.com", "ip", "axis_register_slice"],
     ["xilinx.com", "ip", "axis_data_fifo"],
     ["xilinx.com", "ip", "floating_point"],
+    ["xilinx.com", "module_ref", "prepend_seqnum"],
 ]
 
 opponent = {