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Add Dual Core templates (AC6 only)
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VladimirUmek committed Dec 10, 2024
1 parent 73a971e commit c7fa28b
Showing 32 changed files with 19,759 additions and 0 deletions.
6 changes: 6 additions & 0 deletions NXP.FRDM-MCXN947_BSP.pdsc
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@@ -1798,5 +1798,11 @@
<template name="Simple Board project" path="/boards/frdmmcxn947/cmsis/templates/Board/Simple" file="Simple.csolution.yml" condition="Template_Board">
<description>Single-core project without TrustZone using MCUXpresso configured for FRDM-MCXN947 Board</description>
</template>
<template name="DualCore Board project" path="/boards/frdmmcxn947/cmsis/templates/Board/DualCore" file="DualCore.csolution.yml" condition="Template_Board">
<description>Dual-core project without TrustZone using MCUXpresso configured for FRDM-MCXN947 Board</description>
</template>
<template name="DualCore TrustZone Board project" path="/boards/frdmmcxn947/cmsis/templates/Board/DualCore_TZ" file="DualCore_TZ.csolution.yml" condition="Template_Board">
<description>Dual-core project with TrustZone using MCUXpresso configured for FRDM-MCXN947 Board</description>
</template>
</csolution>
</package>
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solution:
created-for: CMSIS-Toolbox@2.6.0
cdefault:

select-compiler:
- compiler: AC6

compiler: AC6

packs:
- pack: NXP::FRDM-MCXN947_BSP
- pack: NXP::MCXN947_DFP
- pack: ARM::CMSIS

target-types:
- type: MCXN947
board: FRDM-MCXN947
device: NXP::MCXN947VDF

build-types:
- type: Debug
debug: on
optimize: none

- type: Release
debug: off
optimize: balanced

projects:
- project: ./cm33_core1/core1.cproject.yml
- project: ./cm33_core0/core0.cproject.yml
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/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
*.o(.bss.noinit.*)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}

LR_CORE1_IMAGE CORE1_ROM_BASE {
CORE1_REGION CORE1_ROM_BASE CORE1_ROM_SIZE {
* (.core1_code)
}
}

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project:
device: :cm33_core0
processor:
trustzone: secure

generators:
options:
- generator: MCUXpressoConfig
path: ./MCUXpressoConfig
name: ConfigTools

components:
- component: Device:Config Tools:Init
- component: Device:Startup
- component: Device:CMSIS:MCXN947_header
- component: Device:CMSIS:MCXN947_system

- component: Device:SDK Drivers:clock
- component: Device:SDK Drivers:common
- component: Device:SDK Drivers:mcx_spc
- component: Device:SDK Drivers:reset

- component: Device:SDK Utilities:incbin
add-path-asm:
- $OutDir(core1)$

- component: CMSIS:CORE

groups:
- group: Board
files:
- file: ./main.c

setups:
- setup: AC6
for-compiler: AC6
misc:
- Link:
- --keep="*(*core1_code)"

linker:
- regions: ../regions_MCXN947VDF.h
define:
- CPU_MCXN947VDF_cm33_core0
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/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#include "RTE_Components.h"
#include CMSIS_device_header

#include "clock_config.h"
#include "peripherals.h"
#include "pin_mux.h"

int main (void) {

/* System initialization */
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();
BOARD_InitBootPins();

while(1) {
;
}
}
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/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
*.o(.bss.noinit.*)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif

#if __RAM1_SIZE > 0
RW_RAM1 __RAM1_BASE __RAM1_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM2_SIZE > 0
RW_RAM2 __RAM2_BASE __RAM2_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM3_SIZE > 0
RW_RAM3 __RAM3_BASE __RAM3_SIZE {
.ANY (+RW +ZI)
}
#endif
}

#if __ROM1_SIZE > 0
LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 +0 __ROM1_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM2_SIZE > 0
LR_ROM2 __ROM2_BASE __ROM2_SIZE {
ER_ROM2 +0 __ROM2_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM3_SIZE > 0
LR_ROM3 __ROM3_BASE __ROM3_SIZE {
ER_ROM3 +0 __ROM3_SIZE {
.ANY (+RO +XO)
}
}
#endif

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project:
device: :cm33_core1

generators:
options:
- generator: MCUXpressoConfig
path: ./MCUXpressoConfig
name: ConfigTools

components:
- component: Device:Startup
- component: Device:CMSIS:MCXN947_header
- component: Device:CMSIS:MCXN947_system

- component: Device:SDK Drivers:clock
- component: Device:SDK Drivers:common
- component: Device:SDK Drivers:mcx_spc
- component: Device:SDK Drivers:reset

- component: CMSIS:CORE

groups:
- group: Board
files:
- file: ./main.c

linker:
- regions: ../regions_MCXN947VDF.h
define:
- CPU_MCXN947VDF_cm33_core1

output:
base-name: core1_image
type: bin
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@@ -0,0 +1,33 @@
/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#include "RTE_Components.h"
#include CMSIS_device_header

#ifndef CORE1_SYSTEM_CORE_CLOCK
#define CORE1_SYSTEM_CORE_CLOCK 150000000
#endif

int main (void) {

SystemCoreClock = CORE1_SYSTEM_CORE_CLOCK;

while(1) {
;
}
}
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@@ -0,0 +1,85 @@
#ifndef REGIONS_MCXN947VDF_H
#define REGIONS_MCXN947VDF_H

//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
//------ With VS Code: Open Preview for Configuration Wizard -------------------

// <i> Device Family Pack (DFP): NXP::MCXN947_DFP@19.0.0
// <i> Board Support Pack (BSP): NXP::FRDM-MCXN947_BSP@19.1.0-dev19

// <h> Core 0 Memory Configuration
// ===============================
// <o> ROM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains Startup and Vector Table
#define CORE0_ROM_BASE 0x00000000
// <o> ROM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_ROM_SIZE 0x000C0000

// <o> RAM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains uninitialized RAM, Stack, and Heap
#define CORE0_RAM_BASE 0x20000000
// <o> RAM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_RAM_SIZE 0x0004E000

// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE0_STACK_SIZE 0x00000400

// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE0_HEAP_SIZE 0x00010000
// </h>
// </h>

// <h> Core 1 Memory Configuration
// ===============================
// <o> ROM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains Startup and Vector Table
#define CORE1_ROM_BASE 0x000C0000
// <o> ROM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00200000
#define CORE1_ROM_SIZE 0x00040000

// <o> RAM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x20000000
// <i> Contains uninitialized RAM, Stack, and Heap
#define CORE1_RAM_BASE 0x2004E000
// <o> RAM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00068000
#define CORE1_RAM_SIZE 0x0001A000

// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE1_STACK_SIZE 0x00000400

// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE1_HEAP_SIZE 0x00000400
// </h>

//-------- End of configuration section --------

// Map defines to match linker script expectations
#ifdef CPU_MCXN947VDF_cm33_core0
#define __ROM0_BASE CORE0_ROM_BASE
#define __ROM0_SIZE CORE0_ROM_SIZE
#define __RAM0_BASE CORE0_RAM_BASE
#define __RAM0_SIZE CORE0_RAM_SIZE
#define __STACK_SIZE CORE0_STACK_SIZE
#define __HEAP_SIZE CORE0_HEAP_SIZE

#define __ROM1_BASE CORE1_ROM_BASE
#define __ROM1_SIZE CORE1_ROM_SIZE
#endif

#ifdef CPU_MCXN947VDF_cm33_core1
#define __ROM0_BASE CORE1_ROM_BASE
#define __ROM0_SIZE CORE1_ROM_SIZE
#define __RAM0_BASE CORE1_RAM_BASE
#define __RAM0_SIZE CORE1_RAM_SIZE
#define __STACK_SIZE CORE1_STACK_SIZE
#define __HEAP_SIZE CORE1_HEAP_SIZE
#endif

#endif /* REGIONS_MCXN947VDF_H */
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solution:
created-for: CMSIS-Toolbox@2.6.0
cdefault:

select-compiler:
- compiler: AC6

compiler: AC6

packs:
- pack: NXP::FRDM-MCXN947_BSP
- pack: NXP::MCXN947_DFP
- pack: ARM::CMSIS

target-types:
- type: MCXN947
device: NXP::MCXN947VDF
board: NXP::FRDM-MCXN947

build-types:
- type: Debug
debug: on
optimize: none

- type: Release
debug: off
optimize: balanced

projects:
- project: ./cm33_core1/core1.cproject.yml
- project: ./cm33_core0/secure/core0_s.cproject.yml
- project: ./cm33_core0/non-secure/core0_ns.cproject.yml
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/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
*.o(.bss.noinit.*)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}

LR_CORE1_IMAGE CORE1_ROM_BASE {
CORE1_REGION CORE1_ROM_BASE CORE1_ROM_SIZE {
* (.core1_code)
}
}

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project:
device: :cm33_core0
processor:
trustzone: non-secure

components:
- component: Device:Startup
- component: Device:CMSIS:MCXN947_header
- component: Device:CMSIS:MCXN947_system

- component: Device:SDK Drivers:clock
- component: Device:SDK Drivers:common
- component: Device:SDK Drivers:mcx_spc
- component: Device:SDK Drivers:reset

- component: Device:SDK Utilities:incbin
add-path-asm:
- $OutDir(core1)$

- component: CMSIS:CORE

add-path:
- ../secure

groups:
- group: Board
files:
- file: ./main.c

- group: CMSE Library
files:
- file: $cmse-lib(core0_s)$

setups:
- setup: AC6
for-compiler: AC6
misc:
- Link:
- --keep="*(*core1_code)"

linker:
- regions: ../../regions_MCXN947VDF.h
define:
- CPU_MCXN947VDF_cm33_core0
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@@ -0,0 +1,35 @@
/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#include "RTE_Components.h"
#include CMSIS_device_header

#include "secure_lib.h" // Secure library interface

#define CORE0_SYSCLK_FREQ 150000000

void SystemInit (void) {
SystemCoreClock = CORE0_SYSCLK_FREQ;
}

int main (void) {

while(1) {
;
}
}
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@@ -0,0 +1,76 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}
/*
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER __VENEER_BASE __VENEER_SIZE {
*(Veneer$$CMSE)
}
#endif
*/
RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
*.o(.bss.noinit.*)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __VENEER_BASE ALIGN 32 __VENEER_SIZE {

ER_CMSE_VENEER __VENEER_BASE __VENEER_SIZE {
*(Veneer$$CMSE)
}
}
#endif

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project:
device: :cm33_core0
processor:
trustzone: secure

generators:
options:
- generator: MCUXpressoConfig
path: ./MCUXpressoConfig
name: ConfigTools

components:
- component: Device:Config Tools:Init
- component: Device:Startup
- component: Device:CMSIS:MCXN947_header
- component: Device:CMSIS:MCXN947_system

- component: Device:SDK Drivers:clock
- component: Device:SDK Drivers:common
- component: Device:SDK Drivers:mcx_spc
- component: Device:SDK Drivers:reset

- component: CMSIS:CORE

groups:
- group: Board
files:
- file: ./main.c

- group: CMSE Library
files:
- file: ./secure_lib.c
- file: ./secure_lib.h

linker:
- regions: ../../regions_MCXN947VDF.h
define:
- CPU_MCXN947VDF_cm33_core0
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@@ -0,0 +1,106 @@
/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header

#include "clock_config.h"
#include "peripherals.h"
#include "pin_mux.h"
#include "resource_config.h"


/* Start address of the non-secure application */
#ifndef NS_APP_START_ADDRESS
#define NS_APP_START_ADDRESS (0x00020000)
#endif

/* Start address of the core1 application */
#ifndef CORE1_BOOT_ADDRESS
#define CORE1_BOOT_ADDRESS (0x000C0000)
#endif

/* Define a pointer to a function that will be executed in non-secure state */
typedef void (*NS_Func_t) (void) __attribute__((cmse_nonsecure_call));

/*
Boots secondary core.
This function sets the secondary core boot address, enables clock to the core
and releases secondary core from reset.
*/
void core1_enable (uint32_t boot_address) {
uint32_t cpuctrl;

/* Set CPU1 boot source */
SYSCON->CPBOOT = (boot_address & SYSCON_CPBOOT_CPBOOT_MASK);

/* Read out CPU Control register */
cpuctrl = SYSCON->CPUCTRL;
/* Set Write Protect mask, enable CPU1 clock but keep it under reset */
cpuctrl |= (0xC0C4 << 16) | SYSCON_CPUCTRL_CPU1RSTEN_MASK | SYSCON_CPUCTRL_CPU1CLKEN_MASK;
SYSCON->CPUCTRL = cpuctrl;

/* Release CPU1 from reset */
SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CPU1RSTEN_MASK;
}

/*
Switch to the non-secure state.
Fist entry in the non-secure vector table is the Main Stack Pointer:
*((uint32_t *)(NS_APP_START_ADDRESS)) == MSP_NS
Second entry in the non-secure vector table is the Reset Handler:
*((uint32_t *)(NS_APP_START_ADDRESS + 4U)) == Reset_Handler
*/
void nonsecure_app_start (uint32_t ns_app_start_addr) {
uint32_t Stack_NS;
NS_Func_t ResetHandler_NS;

/* Read the address of the main stack in non-secure state */
Stack_NS = *((volatile uint32_t *)(NS_APP_START_ADDRESS));

/* Set Main Stack Pointer for the non-secure side (MSP_NS) */
__TZ_set_MSP_NS(Stack_NS);

/* Set address of the non-secure Reset Handler */
ResetHandler_NS = (NS_Func_t)(*((uint32_t *)(NS_APP_START_ADDRESS + 4U)));

/* Call non-secure Reset Handler and start executing non-secure application */
ResetHandler_NS();
}

int main (void) {

/* System initialization */
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();
BOARD_InitBootPins();
BOARD_InitBootTEE();

/* Boot core1 */
core1_enable(CORE1_BOOT_ADDRESS);

/* Switch to the non-secure application */
nonsecure_app_start(NS_APP_START_ADDRESS);

/* Non-secure application does not return */
for (;;){;}
}
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/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#include <stdint.h>
#include <arm_cmse.h> // CMSE definitions
#include "secure_lib.h" // Header file with secure interface API

#define NON_SECURE_CALLABLE_FUNC __attribute__((cmse_nonsecure_entry))

/* Function that executes in secure state and can be called from non-secure state. */
NON_SECURE_CALLABLE_FUNC int32_t func (uint32_t arg) {
(void)arg;

return (0);
}
Original file line number Diff line number Diff line change
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/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#ifndef SECURE_LIB_H__
#define SECURE_LIB_H__

#include <stdint.h>

/*
Function that executes in secure state and can be called from non-secure state.
*/
int32_t func (uint32_t arg);

#endif /* SECURE_LIB_H__ */
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/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
*.o(.bss.noinit.*)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif

#if __RAM1_SIZE > 0
RW_RAM1 __RAM1_BASE __RAM1_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM2_SIZE > 0
RW_RAM2 __RAM2_BASE __RAM2_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM3_SIZE > 0
RW_RAM3 __RAM3_BASE __RAM3_SIZE {
.ANY (+RW +ZI)
}
#endif
}

#if __ROM1_SIZE > 0
LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 +0 __ROM1_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM2_SIZE > 0
LR_ROM2 __ROM2_BASE __ROM2_SIZE {
ER_ROM2 +0 __ROM2_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM3_SIZE > 0
LR_ROM3 __ROM3_BASE __ROM3_SIZE {
ER_ROM3 +0 __ROM3_SIZE {
.ANY (+RO +XO)
}
}
#endif

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Original file line number Diff line number Diff line change
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project:
device: :cm33_core1

components:
- component: Device:Startup
- component: Device:CMSIS:MCXN947_header
- component: Device:CMSIS:MCXN947_system

- component: Device:SDK Drivers:clock
- component: Device:SDK Drivers:common
- component: Device:SDK Drivers:mcx_spc
- component: Device:SDK Drivers:reset

- component: CMSIS:CORE

groups:
- group: Board
files:
- file: ./main.c

linker:
- regions: ../regions_MCXN947VDF.h
define:
- CPU_MCXN947VDF_cm33_core1

output:
base-name: core1_image
type: bin
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
/*---------------------------------------------------------------------------
* Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*---------------------------------------------------------------------------*/

#include "RTE_Components.h"
#include CMSIS_device_header

#ifndef CORE1_SYSTEM_CORE_CLOCK
#define CORE1_SYSTEM_CORE_CLOCK 150000000
#endif

int main (void) {

SystemCoreClock = CORE1_SYSTEM_CORE_CLOCK;

while(1) {
;
}
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,127 @@
#ifndef REGIONS_MCXN947VDF_H
#define REGIONS_MCXN947VDF_H

//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
//------ With VS Code: Open Preview for Configuration Wizard -------------------

// <i> Device Family Pack (DFP): NXP::MCXN947_DFP@19.0.0
// <i> Board Support Pack (BSP): NXP::FRDM-MCXN947_BSP@19.1.0-dev19

// <h> Core 0 Memory Configuration
// ===============================
// <h> Secure State
// ================
// <o> ROM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains Startup and Vector Table
#define CORE0_S_ROM_BASE 0x10000000
// <o> ROM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_S_ROM_SIZE 0x0001FE00

// <o> Veneers Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x1001FE00
#define CORE0_S_VENEER_BASE (CORE0_S_ROM_BASE + CORE0_S_ROM_SIZE)
// <o> Veneers Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_S_VENEER_SIZE 0x00000200

// <o> RAM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains uninitialized RAM, Stack, and Heap
#define CORE0_S_RAM_BASE 0x30000000
// <o> RAM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_S_RAM_SIZE 0x00008000

// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE0_S_STACK_SIZE 0x00000400

// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE0_S_HEAP_SIZE 0x00000400
// </h>

// <h> Non-secure State
// ====================
// <o> ROM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains Startup and Vector Table
#define CORE0_NS_ROM_BASE 0x00020000
// <o> ROM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_NS_ROM_SIZE 0x000A0000

// <o> RAM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains uninitialized RAM, Stack, and Heap
#define CORE0_NS_RAM_BASE 0x20008000
// <o> RAM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00000000
#define CORE0_NS_RAM_SIZE 0x00046000

// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE0_NS_STACK_SIZE 0x00000400

// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE0_NS_HEAP_SIZE 0x00010000
// </h>
// </h>

// <h> Core 1 Memory Configuration
// ===============================
// <o> ROM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x00000000
// <i> Contains Startup and Vector Table
#define CORE1_ROM_BASE 0x000C0000
// <o> ROM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00200000
#define CORE1_ROM_SIZE 0x00040000

// <o> RAM Base Address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region. Default: 0x20000000
// <i> Contains uninitialized RAM, Stack, and Heap
#define CORE1_RAM_BASE 0x2004E000
// <o> RAM Region Size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region. Default: 0x00068000
#define CORE1_RAM_SIZE 0x0001A000

// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE1_STACK_SIZE 0x00000400

// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define CORE1_HEAP_SIZE 0x00000400
// </h>

//-------- End of configuration section --------

// Map defines to match linker script expectations
#ifdef CPU_MCXN947VDF_cm33_core0
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __ROM0_BASE CORE0_S_ROM_BASE
#define __ROM0_SIZE CORE0_S_ROM_SIZE
#define __RAM0_BASE CORE0_S_RAM_BASE
#define __RAM0_SIZE CORE0_S_RAM_SIZE
#define __STACK_SIZE CORE0_S_STACK_SIZE
#define __HEAP_SIZE CORE0_S_HEAP_SIZE
#define __VENEER_BASE CORE0_S_VENEER_BASE
#define __VENEER_SIZE CORE0_S_VENEER_SIZE
#else
#define __ROM0_BASE CORE0_NS_ROM_BASE
#define __ROM0_SIZE CORE0_NS_ROM_SIZE
#define __RAM0_BASE CORE0_NS_RAM_BASE
#define __RAM0_SIZE CORE0_NS_RAM_SIZE
#define __STACK_SIZE CORE0_NS_STACK_SIZE
#define __HEAP_SIZE CORE0_NS_HEAP_SIZE
#endif
#endif

#ifdef CPU_MCXN947VDF_cm33_core1
#define __ROM0_BASE CORE1_ROM_BASE
#define __ROM0_SIZE CORE1_ROM_SIZE
#define __RAM0_BASE CORE1_RAM_BASE
#define __RAM0_SIZE CORE1_RAM_SIZE
#define __STACK_SIZE CORE1_STACK_SIZE
#define __HEAP_SIZE CORE1_HEAP_SIZE
#endif

#endif /* REGIONS_MCXN947VDF_H */

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