fpga-can

A CAN 2.0B Controller for FPGAs written in Verilog

Small enough that it'll fit on an ICE 40 (~700 LUTs for a minimal transceiver).

Progress

Minimum Viable Project (an error passive node)

• Sample Sync Machine (Connects directly to rx & tx lines and handles resyncing)
  • Written
  • Test Benched
• Rx Pipeline (Bit Unstuffer)
  • Written
  • Test Benched
• Tx Pipeline (Bit Stuffer)
  • Written
  • Test Benched
• CRC Machine (Same for Receiver and Sender)
  • Written
  • Rewritten
  • Test Benched
• Send Machine (Gets told what to send and when to send it)
  • Written
  • Test Benched
• Message Reciever (Takes in the rx pipeline and keeps track of the buses current state)
  • Written
  • Integrated with all the changes I made since I wrote it
  • Test Benched
  • Add all the error counting triggers
• Message Sender (Takes in a msg id and up to 8 bytes and constructs & sends a CAN frame)
  • Written
  • Test Benched
• Tested and Ready to go on actual hardware
  • Zero Warnings Synthesis
  • Passes Test Benches with Changes
  • Hardware implementation confirmed by logic analyzer
• Configurable Msg Latch
  • Written
• Configurable Msg FIFO
  • Written
  • Test Benched

More Features I want to finish (to meet the whole spec)

• Error Counting Machine
  • Written
  • Test Benched

Usage

Test benches can be run with iverilog -o tb tb.v can.v; vvp tb -lxt2 and viewed with gtkwave.

Source Code should be easy to add into an existing verilog project once its done.