xilpm: versal: server: Remove XRAM axi-lite clock selection

Currently tools doesn't support enabling XRAM AXILITE interface so remove XRAM_APB_CLK configuration which selects AXILITE PL source. Signed-off-by: Nicole Baze <[email protected]> Acked-by: Arun Kannan <[email protected]>
Xilinx · Oct 12, 2023 · c9a0ee3 · c9a0ee3
1 parent bd49744
commit c9a0ee3
Showing 1 changed file with 0 additions and 7 deletions.
diff --git a/lib/sw_services/xilpm/src/versal/server/xpm_domain_iso.c b/lib/sw_services/xilpm/src/versal/server/xpm_domain_iso.c
@@ -652,13 +652,6 @@ XStatus XPmDomainIso_Control(u32 IsoIdx, u32 Enable)
 				XPm_RMW32(XPmDomainIso_List[IsoIdx].Node.BaseAddress,
 					  Mask, 0U);
 			}
-
-			if ((u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE == IsoIdx) {
-				/* Select AXI lite clock from PL */
-				XPm_RMW32(XRAM_SLCR_BASEADDR + XRAM_SLCR_APB_CLK_OFFSET,
-					  XRAM_SLCR_APB_CLK_SRC_AXI_LITE_CLK_MASK,
-					  XRAM_SLCR_APB_CLK_SRC_AXI_LITE_CLK_MASK);
-			}
 		} else {
 			if (((u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0 <= IsoIdx) &&
 			    ((u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE >= IsoIdx)) {