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Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1925: Pull request #1213 synchronize by auphelia
October 15, 2024 17:45 15m 35s feature/pyxsi_integration
October 15, 2024 17:45 15m 35s
Analytical FIFO sizing
QuicktestPRAgainstDev #1924: Pull request #1185 synchronize by lstasytis
October 15, 2024 16:10 14m 30s lstasytis:feature/analytical-fifo-sizing
October 15, 2024 16:10 14m 30s
Analytical FIFO sizing
QuicktestPRAgainstDev #1923: Pull request #1185 synchronize by lstasytis
October 15, 2024 16:09 Action required lstasytis:feature/analytical-fifo-sizing
October 15, 2024 16:09 Action required
Analytical FIFO sizing
QuicktestPRAgainstDev #1922: Pull request #1185 synchronize by lstasytis
October 15, 2024 15:33 Action required lstasytis:feature/analytical-fifo-sizing
October 15, 2024 15:33 Action required
Analytical FIFO sizing
QuicktestPRAgainstDev #1921: Pull request #1185 synchronize by lstasytis
October 15, 2024 15:31 Action required lstasytis:feature/analytical-fifo-sizing
October 15, 2024 15:31 Action required
4-BIT DSP-MVU: Allow very wide lanes requiring even a high-lane extension.
QuicktestPRAgainstDev #1920: Pull request #1203 synchronize by preusser
October 15, 2024 15:19 15m 22s tpreusse.mvu_harden
October 15, 2024 15:19 15m 22s
Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1919: Pull request #1213 synchronize by auphelia
October 14, 2024 12:50 15m 57s feature/pyxsi_integration
October 14, 2024 12:50 15m 57s
Merge pull request #1212 from Xilinx/hotfix/tutorial
QuicktestPRAgainstDev #1918: Commit ac2fa5a pushed by auphelia
October 11, 2024 15:59 15m 14s dev
dev
October 11, 2024 15:59 15m 14s
Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1917: Pull request #1213 synchronize by auphelia
October 11, 2024 15:59 12m 29s feature/pyxsi_integration
October 11, 2024 15:59 12m 29s
Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1916: Pull request #1213 synchronize by auphelia
October 11, 2024 09:54 12m 29s feature/pyxsi_integration
October 11, 2024 09:54 12m 29s
Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1915: Pull request #1213 synchronize by auphelia
October 11, 2024 09:53 12m 3s feature/pyxsi_integration
October 11, 2024 09:53 12m 3s
Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1914: Pull request #1213 synchronize by auphelia
October 11, 2024 09:49 12m 15s feature/pyxsi_integration
October 11, 2024 09:49 12m 15s
Pyxsi enablement for alternative rtl simulation
QuicktestPRAgainstDev #1913: Pull request #1213 opened by auphelia
October 11, 2024 09:45 12m 11s feature/pyxsi_integration
October 11, 2024 09:45 12m 11s
Update folding configuration for FPGA flow tutorial
QuicktestPRAgainstDev #1912: Pull request #1212 synchronize by auphelia
October 11, 2024 09:36 15m 20s hotfix/tutorial
October 11, 2024 09:36 15m 20s
Update folding configuration for FPGA flow tutorial
QuicktestPRAgainstDev #1911: Pull request #1212 opened by auphelia
October 11, 2024 08:48 15m 10s hotfix/tutorial
October 11, 2024 08:48 15m 10s
Feature/conv ext weights
QuicktestPRAgainstDev #1910: Pull request #1132 synchronize by mdanilow
October 10, 2024 16:19 Action required mdanilow:feature/conv_ext_weights
October 10, 2024 16:19 Action required
Add support for Host Memory Access
QuicktestPRAgainstDev #1909: Pull request #1210 opened by LinusJungemann
October 9, 2024 12:13 Action required LinusJungemann:feature/host-memory-access
October 9, 2024 12:13 Action required
Merge pull request #1030 from iksnagreb/fix/round-and-clip-thresholds
QuicktestPRAgainstDev #1908: Commit 8da09eb pushed by auphelia
October 7, 2024 10:47 14m 55s dev
dev
October 7, 2024 10:47 14m 55s
4-BIT DSP-MVU: Allow very wide lanes requiring even a high-lane extension.
QuicktestPRAgainstDev #1907: Pull request #1203 opened by preusser
September 30, 2024 07:01 14m 29s tpreusse.mvu_harden
September 30, 2024 07:01 14m 29s
Fix RoundAndClipThresholds Transformation
QuicktestPRAgainstDev #1906: Pull request #1030 synchronize by auphelia
September 27, 2024 14:36 15m 47s iksnagreb:fix/round-and-clip-thresholds
September 27, 2024 14:36 15m 47s
InsertDWC and multiple input/output nodes
QuicktestPRAgainstDev #1904: Pull request #1201 opened by mdanilow
September 26, 2024 16:05 14m 28s mdanilow:fix/branched_dwc
September 26, 2024 16:05 14m 28s
Merge pull request #1188 from mdanilow/fix/branched_structures
QuicktestPRAgainstDev #1903: Commit ab1c721 pushed by auphelia
September 26, 2024 16:04 14m 13s dev
dev
September 26, 2024 16:04 14m 13s
Fix RoundAndClipThresholds Transformation
QuicktestPRAgainstDev #1902: Pull request #1030 synchronize by auphelia
September 26, 2024 13:20 14m 41s iksnagreb:fix/round-and-clip-thresholds
September 26, 2024 13:20 14m 41s
Fix RoundAndClipThresholds Transformation
QuicktestPRAgainstDev #1901: Pull request #1030 synchronize by auphelia
September 26, 2024 11:57 15m 38s iksnagreb:fix/round-and-clip-thresholds
September 26, 2024 11:57 15m 38s
Fix RoundAndClipThresholds Transformation
QuicktestPRAgainstDev #1900: Pull request #1030 synchronize by auphelia
September 26, 2024 10:44 15m 21s iksnagreb:fix/round-and-clip-thresholds
September 26, 2024 10:44 15m 21s