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Fix redeclaration of streams in StreamingDataWidthConverter_hls #1107

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merged 4 commits into from
Jun 19, 2024
Merged

Fix redeclaration of streams in StreamingDataWidthConverter_hls #1107

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a325a5f
[StreamingDataWidthConverter_hls] Remove duplicate intermediate stream
iksnagreb Jun 14, 2024
7b80e1a
[StreamingDataWidthConverter_hls] Remove the other duplicate stream
iksnagreb Jun 14, 2024
6fd8b1a
Merge remote-tracking branch 'upstream/dev' into fix/streaming_data_w…
auphelia Jun 19, 2024
961e48b
[Tests] Update dwc testing to test rtl and hls variant
auphelia Jun 19, 2024
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6 changes: 0 additions & 6 deletions src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py
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Original file line number Diff line number Diff line change
Expand Up @@ -78,12 +78,6 @@ def strm_decl(self):
self.get_instream_width(), self.hls_sname(), self.hls_sname()
)
)
if self.needs_lcm():
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> intermediate ("intermediate");'.format(
self.get_iowidth_lcm()
)
)
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> out_{} ("out_{}");'.format(
self.get_outstream_width(), self.hls_sname(), self.hls_sname()
Expand Down
17 changes: 8 additions & 9 deletions tests/fpgadataflow/test_fpgadataflow_dwc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@
from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers


def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype):
def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style):
inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape)
outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, shape)

Expand All @@ -63,6 +63,7 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype):
inWidth=inWidth,
outWidth=outWidth,
dataType=str(finn_dtype.name),
preferred_impl_style=impl_style,
)

graph = helper.make_graph(nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp])
Expand All @@ -86,25 +87,25 @@ def prepare_inputs(input_tensor, dt):
([1, 24], 6, 4, DataType["INT2"]),
([1, 24], 4, 6, DataType["INT2"]),
([1, 4], 2, 4, DataType["BIPOLAR"]),
([1, 2, 8], 2, 4, DataType["BIPOLAR"]),
([1, 4], 4, 2, DataType["INT2"]),
([1, 2, 8], 4, 4, DataType["INT2"]),
([1, 2, 8], 8, 16, DataType["INT2"]),
],
)
@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"])
@pytest.mark.parametrize("impl_style", ["hls", "rtl"])
@pytest.mark.fpgadataflow
@pytest.mark.slow
@pytest.mark.vivado
def test_fpgadataflow_dwc(config, exec_mode):
def test_fpgadataflow_dwc(config, exec_mode, impl_style):
shape, inWidth, outWidth, finn_dtype = config

test_fpga_part = "xc7z020clg400-1"
# generate input data
x = gen_finn_dt_tensor(finn_dtype, shape)
input_dict = prepare_inputs(x, finn_dtype)

model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype)
model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style)
# verify abstraction level execution
y = oxe.execute_onnx(model, input_dict)["outp"]
assert (
Expand Down Expand Up @@ -136,19 +137,17 @@ def test_fpgadataflow_dwc(config, exec_mode):
@pytest.mark.parametrize(
"config",
[
([1, 24], 6, 4, DataType["INT2"]),
([1, 24], 4, 6, DataType["INT2"]),
([1, 4], 2, 4, DataType["BIPOLAR"]),
([1, 2, 8], 2, 4, DataType["BIPOLAR"]),
([1, 4], 4, 2, DataType["INT2"]),
([1, 2, 8], 4, 4, DataType["INT2"]),
([1, 2, 8], 8, 16, DataType["INT2"]),
],
)
@pytest.mark.parametrize("impl_style", ["hls", "rtl"])
@pytest.mark.fpgadataflow
@pytest.mark.slow
@pytest.mark.vivado
def test_fpgadataflow_dwc_stitched_rtlsim(config):
def test_fpgadataflow_dwc_stitched_rtlsim(config, impl_style):
shape, inWidth, outWidth, finn_dtype = config

test_fpga_part = "xc7z020clg400-1"
Expand All @@ -157,7 +156,7 @@ def test_fpgadataflow_dwc_stitched_rtlsim(config):
x = gen_finn_dt_tensor(finn_dtype, shape)
input_dict = prepare_inputs(x, finn_dtype)

model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype)
model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style)
model = model.transform(SpecializeLayers(test_fpga_part))
model = model.transform(InsertFIFO(create_shallow_fifos=True))
model = model.transform(SpecializeLayers(test_fpga_part))
Expand Down
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