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Release merge for v0.10.1 #1123
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…ore default transformation steps tested
Note: This was already implemented, it was just not called from the step_synthesize_bitfile.
According to the last synthesis I ran using Vitis/Vivado 2022.2, the DSP48 utilization seems to be reported in row 10 of the XML table.
Signed-off-by: aziz bahri <[email protected]>
Signed-off-by: aziz bahri <[email protected]>
…test Extension to end2end mobilenet test
[Threshold RTL] padd threshold steps based on activation bitwidth
…and count in FIFO template
Signed-off-by: Jonas Kühle <[email protected]>
Signed-off-by: Jonas Kühle <[email protected]>
Signed-off-by: Jonas Kühle <[email protected]>
Bug fix for FIFO count range mismatch between Python and RTL
Helper function for reading numpy files into hls::vector
Update xrt download command in Dockerfile
Enable optional xrt installation from local deb
Fix fast data packing for rtlsim
Install setupstools explicitly in Dockerfile
Expose DSP variant for RTL MVU
[Deps] Update finn-experimental commit hash
…idth_converter_hls-duplicate-stream
…erter_hls-duplicate-stream Fix redeclaration of streams in StreamingDataWidthConverter_hls
Optimizing resources for per tensor quantization
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