DCE

The DCE (Dynamic Clock Enable) primitive, also known as Global Clock 3.1 DCE, enables or disables the internal logic clocked by the GCLK network dynamically. When disabled, it reduces power consumption by stopping the slew of all logic driven by this clock. It has three ports: CLKIN for input clock signal, CE for clock enable signal (active-high), and CLKOUT for output clock signal.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CE	1	input
CLKIN	1	input
CLKOUT	1	output

Verilog Instantiation

DCE dce_inst (
    .CE(CE),
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);