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Merge pull request #9 from abs-tudelft/chore/module-revamp
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Create an external module version of TydiModule.
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ccromjongh authored Mar 20, 2024
2 parents f5c1171 + f69f6b3 commit e5f14c0
Showing 1 changed file with 15 additions and 9 deletions.
24 changes: 15 additions & 9 deletions src/main/scala/nl/tudelft/tydi_chisel/TydiLib.scala
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@ import scala.collection.mutable
import scala.collection.mutable.ListBuffer

import chisel3._
import chisel3.experimental.{BaseModule, ExtModule}
import chisel3.internal.firrtl.Width
import chisel3.util.{log2Ceil, Cat}
import nl.tudelft.tydi_chisel.ReverseTranspiler._
Expand Down Expand Up @@ -395,7 +396,7 @@ class PhysicalStream(private val e: TydiEl, n: Int = 1, d: Int = 0, c: Int, priv
this.user := bundle.user
}

def processWith[T <: SubProcessorSignalDef](module: => T)(implicit parentModule: TydiModule): PhysicalStream = {
def processWith[T <: SubProcessorSignalDef](module: => T)(implicit parentModule: TydiModuleMixin): PhysicalStream = {
val processingModule = parentModule.Module(module)
processingModule.in := this
processingModule.out
Expand All @@ -406,13 +407,13 @@ class PhysicalStream(private val e: TydiEl, n: Int = 1, d: Int = 0, c: Int, priv
module.out
}

def convert(memSize: Int)(implicit parentModule: TydiModule): PhysicalStream = {
def convert(memSize: Int)(implicit parentModule: TydiModuleMixin): PhysicalStream = {
val processingModule = parentModule.Module(new ComplexityConverter(this, memSize))
processingModule.in := this
processingModule.out
}

def duplicate(k: Int)(implicit parentModule: TydiModule): Vec[PhysicalStream] = {
def duplicate(k: Int)(implicit parentModule: TydiModuleMixin): Vec[PhysicalStream] = {
val processingModule = parentModule.Module(new StreamDuplicator(k, this))
processingModule.in := this
processingModule.out
Expand Down Expand Up @@ -610,19 +611,21 @@ object PhysicalStreamDetailed {
): PhysicalStreamDetailed[Tel, Tus] = Wire(new PhysicalStreamDetailed(e, n, d, c, r, u))
}

class TydiModule extends Module with TranspileExtend {
trait TydiModuleMixin extends BaseModule with TranspileExtend {
implicit var parentModule: TydiModuleMixin = this

implicit var parentModule: TydiModule = this

private val moduleList = ListBuffer[TydiModule]()
private val moduleList = ListBuffer[TydiModuleMixin]()

def mount[Tel <: TydiEl, Tus <: Data](bundle: PhysicalStreamDetailed[Tel, Data], io: PhysicalStream): Unit = {
io := bundle
}

def Module[T <: TydiModule](bc: => T): T = {
def Module[T <: BaseModule](bc: => T): T = {
val v = chisel3.Module.apply(bc)
moduleList += v
// If we are actually dealing with a TydiModule, add it to our module list.
v match {
case v: TydiModuleMixin => moduleList += v
}
v
}

Expand Down Expand Up @@ -702,3 +705,6 @@ class TydiModule extends Module with TranspileExtend {

override def fingerprint: String = this.name
}

abstract class TydiModule extends Module with TydiModuleMixin
abstract class TydiExtModule extends ExtModule with TydiModuleMixin

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