VHDL Generation #177

matthijsr · 2021-08-31T15:47:11Z

VHDL Generation.

Fixes invalid VHDL generated for packages (use correct record type syntax, add usings)
Fixes mismatch between canonical and "fancy" components. (Now uses arrays for multiple element lanes. Would previously only represent the data of a single element for the "fancy" declaration.)
Introduces rudimentary architecture generation
Introduces utilities to map between complex VHDL objects and between flat (bit vector) and complex objects
Introduces wrapper generation for "fancy" declarations of streamlets. (Architecture declaration of canonical component as entity, mapped to fancy component.)

To do/improve:

Expand VHDL generation (support functions, procedures, processes and associated logic)
Resolve edge cases for mapping between fancy and canonical declarations. (Mainly unions.)
Correctly validate the mode/state of objects. (Avoid using an output to drive an output, for example.)

Required changes (beyond code quality/functionality):

Squash Akos's commits
Squash my own commits?
Remove Dot graph and Chisel generation, Pest grammar. (Should be a separate PR, if desired.)
Change generation tests back to output to a tmpdir, rather than an actual folder. (Used for VHDL verification.)
Undo dependabot.yml change
Remove any other cruft that may have been (re)introduced (e.g., src/design/implementation/composer/misc.rs)
Reorganize where all of this goes? (stdlib might not be a suitable location/name)

Before cargo fix Sleepy :( Dot toy example Cargo fix Save Save2 Working test from parser to dot Map example Dot color scheme Composition checkpoint + new frontend WIP WIP parser composition checkpoint Grammar features Grammar features Group split More miracle Map half done Map to show Map demo Example Chisel backend initial commit Added support for Decoupled Before anything happens :( Carfo fix Chisel backend fixes Checkpoint before the doom Checkpoint before streamlet implementation restructuring Big milestone before zzzzz Checkpoint Reduce working Happy hour Beautify Test restructuring Debug cleanup Example with all parallel patterns Test fix Refactoring Spark example Before grammar modification Thesis version

…t fixes). This will serve as my main branch for the time being.

…ail, otherwise.) When Port/Componentifying things, also order by inputs first, then outputs.

…look into that some more.

… won't work.)

…fier to with_throughput instead

…at's out of scope for now.

…le assignment between otherwise identical record types with different names.

… same signal, however...

…e to_flat solution is incorrect.

…d to figure out how to consistently determine the relation between fancy and canonical ports.

…ecture generation.

… to up/dn types.

…types from splittable types.

… update. Remove vhdl_constructs folder.

…ant.

matthijsr · 2021-10-07T13:29:23Z

I've removed anything I know for sure I don't need or use.
There's a few additions and changes from Akos's branch (mainly in the design module, such as GenericComponent and the changes to Project and Library) which I don't strictly need, but I have been using throughout my code. So that would take a fair bit more refactoring.

ahadnagy and others added 30 commits September 23, 2021 15:52

Branch off from new_grammar, merge abs-tudelft/master (manual conflic…

a76531b

…t fixes). This will serve as my main branch for the time being.

Dependencies, dependabot

fcb11b4

Some initial concepts.

c88ccb0

Reorganize module a bit, try out VHDL package generation

f7d6d81

Stub can be source, sink or passthrough.

66be8f4

Test error as well

c02db14

Refactoring, move ImplementationBackend to its own module.

a75e401

Store interfaces in BTreeMap to ensure they are ordered. (Tests may f…

58622b9

…ail, otherwise.) When Port/Componentifying things, also order by inputs first, then outputs.

Try out some vhdl generation. Change record declaration syntax.

f098e96

Declare usings when declaring package

4b6c4ad

Unions and higher throughput doesn't seem to be converted correctly, …

ba5dde6

…look into that some more.

Trying some VHDL constructs to make unions easier to work with. (This…

83b4cf5

… won't work.)

This looks to be the only real solution

7813ecc

Just let stubs handle anything that gets thrown at them.

b3be13e

Need to consider how to set up arrays, think I might just pass identi…

10caca8

…fier to with_throughput instead

Like so, probably.

6d845ff

Generate array declarations. This broke Chisel, unfortunately, but th…

7d5817b

…at's out of scope for now.

Overlooked a match

fa545c9

Refactor ports declaration, re-use for entity declaration.

f93c7de

Some preliminary notes on architecture generation

d62b9a9

Some more preliminary notes on architecture generation

e723abc

Refactoring usings, stdlib common organization

c80b37e

Further refactoring, usings for Architecture

317c854

Architecture declaration

2bd083e

enum might make sense for arch declarations

2752b44

Slightly more variety in generating package

f9dd733

Make arrays "... to ..." instead of "... downto ..."

03e49a7

Revert array changes, make note for myself.

a0a6e60

fmt

9106fcb

matthijsr added 23 commits September 23, 2021 15:52

All checks done, give up on mode checks for now.

5b186c4

Declarations galore

a8effad

Port mapping declarations

281468c

Convert records object assignments to full record assignments to hand…

19a1b40

…le assignment between otherwise identical record types with different names.

Enable unwrapping array assignments as well, and combine both methods.

40403c3

Work on the wrapper, need to support flattening/unflattening first.

3fd9186

Clean up unused imports to reduce warnings

d377dad

Flattening arrays works

38c5565

Concat LSB-first. Union handling

01b59cb

Unions kinda work, need to be rewritten not to assign multiple to the…

3c7c454

… same signal, however...

Split to_complex solution off for unions, add note indicating that th…

9f0811f

…e to_flat solution is incorrect.

Flattening is as good as it's gonna get for the time being. Still nee…

10cc21f

…d to figure out how to consistently determine the relation between fancy and canonical ports.

At least use what I've got to show off some more comprehensive archit…

00d8320

…ecture generation.

Remove unnecessary port map.

9cbb44c

Fix tests that broke due to union

bbc5108

Fancy wrapper works, but port mapping from signals is complicated due…

05b970f

… to up/dn types.

Make sure arrays split correctly, function to create separate object …

8a149dc

…types from splittable types.

VHDL generation now generates wrappers for fancy variants of components

336745a

Rebased again, just ignored Cargo.lock, then deleted it and ran cargo…

21046f6

… update. Remove vhdl_constructs folder.

Once again, rebase and fix up cargo.lock

baf083c

Remove most of Akos's generator code. Make sure cargo test passes.

6887ce5

Cargo fix. Remove unused imports. Allow two instances of dead code.

b04b1c0

cargo fmt

13e5291

matthijsr force-pushed the stdlib/develop branch from e0a78aa to 13e5291 Compare September 23, 2021 13:52

matthijsr added 5 commits September 23, 2021 15:57

Revert logo change

f68d6ee

Merge remote-tracking branch 'abs/master' into stdlib/develop

7a0a91b

Remove unused dependencies

e82dcb3

Remove some playground tests, replace prints with asserts where relev…

98fc91c

…ant.

Test file generation with tempdir

25582f1

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VHDL Generation #177

VHDL Generation #177

matthijsr commented Aug 31, 2021 •

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matthijsr commented Oct 7, 2021

VHDL Generation #177

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VHDL Generation #177

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matthijsr commented Aug 31, 2021 •

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