Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Refactor hw debug aarch32 attempt2 #10

Open
wants to merge 4 commits into
base: master
Choose a base branch
from
Open

Refactor hw debug aarch32 attempt2 #10

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
268e3bf
split arm/machine/debug.c
alwin-joshy Feb 15, 2024
21191d1
split arm/machine/debug.c
alwin-joshy Feb 15, 2024
8c8170c
change files to allow compilation
alwin-joshy Feb 15, 2024
00e378e
hw debug api: aarch64 port
alwin-joshy Feb 16, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions include/api/syscall.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@ exception_t handleInterruptEntry(void);
exception_t handleUnknownSyscall(word_t w);
exception_t handleUserLevelFault(word_t w_a, word_t w_b);
exception_t handleVMFaultEvent(vm_fault_type_t vm_faultType);
exception_t handleDebugFaultEvent(word_t esr);

static inline word_t PURE getSyscallArg(word_t i, word_t *ipc_buffer)
{
Expand Down
149 changes: 131 additions & 18 deletions include/arch/arm/arch/32/mode/machine/debug.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -167,28 +167,141 @@ bool_t isDebugFault(word_t hsr_or_fsr);
*/
seL4_Fault_t handleUserLevelDebugException(word_t fault_vaddr);

/** These next two functions are part of some state flags.
*
* A bitfield of all currently enabled breakpoints for a thread is kept in that
* thread's TCB. These two functions here set and unset the bits in that
* bitfield.
#endif /* CONFIG_HARDWARE_DEBUG_API */

#endif /* !__ASSEMBLER__ */

#endif /* defined(CONFIG_DEBUG_BUILD) || defined (CONFIG_HARDWARE_DEBUG_API) */

#ifdef ARM_BASE_CP14_SAVE_AND_RESTORE

#define MAKE_P14(crn, crm, opc2) "p14, 0, %0, c" #crn ", c" #crm ", " #opc2
#define MAKE_DBGBVR(num) MAKE_P14(0, num, 4)
#define MAKE_DBGBCR(num) MAKE_P14(0, num, 5)
#define MAKE_DBGWVR(num) MAKE_P14(0, num, 6)
#define MAKE_DBGWCR(num) MAKE_P14(0, num, 7)
#define MAKE_DBGXVR(num) MAKE_P14(1, num, 1)

/** Generates read functions for the CP14 control and value registers.
*/
static inline void setBreakpointUsedFlag(tcb_t *t, uint16_t bp_num)
{
if (t != NULL) {
t->tcbArch.tcbContext.breakpointState.used_breakpoints_bf |= BIT(bp_num);
}
#define DEBUG_GENERATE_READ_FN(_name, _reg) \
static inline word_t \
_name(uint16_t bp_num) \
{ \
word_t ret; \
\
switch (bp_num) { \
case 1: \
MRC(MAKE_ ## _reg(1), ret); \
return ret; \
case 2: \
MRC(MAKE_ ## _reg(2), ret); \
return ret; \
case 3: \
MRC(MAKE_ ## _reg(3), ret); \
return ret; \
case 4: \
MRC(MAKE_ ## _reg(4), ret); \
return ret; \
case 5: \
MRC(MAKE_ ## _reg(5), ret); \
return ret; \
case 6: \
MRC(MAKE_ ## _reg(6), ret); \
return ret; \
case 7: \
MRC(MAKE_ ## _reg(7), ret); \
return ret; \
case 8: \
MRC(MAKE_ ## _reg(8), ret); \
return ret; \
case 9: \
MRC(MAKE_ ## _reg(9), ret); \
return ret; \
case 10: \
MRC(MAKE_ ## _reg(10), ret); \
return ret; \
case 11: \
MRC(MAKE_ ## _reg(11), ret); \
return ret; \
case 12: \
MRC(MAKE_ ## _reg(12), ret); \
return ret; \
case 13: \
MRC(MAKE_ ## _reg(13), ret); \
return ret; \
case 14: \
MRC(MAKE_ ## _reg(14), ret); \
return ret; \
case 15: \
MRC(MAKE_ ## _reg(15), ret); \
return ret; \
default: \
assert(bp_num == 0); \
MRC(MAKE_ ## _reg(0), ret); \
return ret; \
} \
}

static inline void unsetBreakpointUsedFlag(tcb_t *t, uint16_t bp_num)
{
if (t != NULL) {
t->tcbArch.tcbContext.breakpointState.used_breakpoints_bf &= ~BIT(bp_num);
}
/** Generates write functions for the CP14 control and value registers.
*/
#define DEBUG_GENERATE_WRITE_FN(_name, _reg) \
static inline void \
_name(uint16_t bp_num, word_t val) \
{ \
switch (bp_num) { \
case 1: \
MCR(MAKE_ ## _reg(1), val); \
return; \
case 2: \
MCR(MAKE_ ## _reg(2), val); \
return; \
case 3: \
MCR(MAKE_ ## _reg(3), val); \
return; \
case 4: \
MCR(MAKE_ ## _reg(4), val); \
return; \
case 5: \
MCR(MAKE_ ## _reg(5), val); \
return; \
case 6: \
MCR(MAKE_ ## _reg(6), val); \
return; \
case 7: \
MCR(MAKE_ ## _reg(7), val); \
return; \
case 8: \
MCR(MAKE_ ## _reg(8), val); \
return; \
case 9: \
MCR(MAKE_ ## _reg(9), val); \
return; \
case 10: \
MCR(MAKE_ ## _reg(10), val); \
return; \
case 11: \
MCR(MAKE_ ## _reg(11), val); \
return; \
case 12: \
MCR(MAKE_ ## _reg(12), val); \
return; \
case 13: \
MCR(MAKE_ ## _reg(13), val); \
return; \
case 14: \
MCR(MAKE_ ## _reg(14), val); \
return; \
case 15: \
MCR(MAKE_ ## _reg(15), val); \
return; \
default: \
assert(bp_num == 0); \
MCR(MAKE_ ## _reg(0), val); \
return; \
} \
}

#endif /* CONFIG_HARDWARE_DEBUG_API */

#endif /* !__ASSEMBLER__ */

#endif /* defined(CONFIG_DEBUG_BUILD) || defined (CONFIG_HARDWARE_DEBUG_API) */
#endif /* ARM_BASE_CP14_SAVE_AND_RESTORE */
25 changes: 13 additions & 12 deletions include/arch/arm/arch/32/mode/object/structures.bf
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -549,13 +549,13 @@ block dbg_bcr {
padding 3
field addressMask 5
field breakpointType 4
field linkedBrp 4
field secureStateControl 2
field hypeModeControl 1
field lbn 4
field ssc 2
field hmc 1
padding 4
field byteAddressSelect 4
field bas 4
padding 2
field supervisorAccess 2
field pmc 2
field enabled 1
}

Expand All @@ -564,15 +564,16 @@ block dbg_wcr {
padding 3
field addressMask 5
padding 3
field enableLinking 1
field linkedBrp 4
field secureStateControl 2
field hypeModeControl 1
field byteAddressSelect 8
field loadStore 2
field supervisorAccess 2
field watchpointType 1
field lbn 4
field ssc 2
field hmc 1
field bas 8
field lsc 2
field pac 2
field enabled 1
}

#endif /* CONFIG_HARDWARE_DEBUG_API */

#include <sel4/arch/shared_types.bf>
4 changes: 4 additions & 0 deletions include/arch/arm/arch/64/mode/fastpath/fastpath.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,10 @@ static inline void NORETURN FORCE_INLINE fastpath_restore(word_t badge, word_t m

c_exit_hook();

#ifdef ARM_CP14_SAVE_AND_RESTORE_NATIVE_THREADS
restore_user_debug_context(cur_thread);
#endif

#ifdef CONFIG_HAVE_FPU
lazyFPURestore(cur_thread);
#endif /* CONFIG_HAVE_FPU */
Expand Down
133 changes: 133 additions & 0 deletions include/arch/arm/arch/64/mode/machine/debug.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,137 @@

#pragma once

#ifdef ARM_BASE_CP14_SAVE_AND_RESTORE

void arch_restore_user_debug_context(tcb_t *target_thread);

/** Determines and carries out what needs to be done for a debug exception.
*
* This could be handling a single-stepping exception, or a breakpoint or
* watchpoint.
*/
seL4_Fault_t handleUserLevelDebugException(word_t esr, word_t fault_vaddr);
bool_t isDebugFault(word_t esr);

#define MAKE_DBGBVR(num) "DBGBVR" #num "_EL1"
#define MAKE_DBGBCR(num) "DBGBCR" #num "_EL1"
#define MAKE_DBGWVR(num) "DBGWVR" #num "_EL1"
#define MAKE_DBGWCR(num) "DBGWCR" #num "_EL1"

/** Generates read functions for the CP14 control and value registers.
*/
#define DEBUG_GENERATE_READ_FN(_name, _reg) \
static inline word_t _name(uint16_t bp_num) { \
word_t ret; \
\
switch (bp_num) { \
case 1: \
MRS(MAKE_##_reg(1), ret); \
return ret; \
case 2: \
MRS(MAKE_##_reg(2), ret); \
return ret; \
case 3: \
MRS(MAKE_##_reg(3), ret); \
return ret; \
case 4: \
MRS(MAKE_##_reg(4), ret); \
return ret; \
case 5: \
MRS(MAKE_##_reg(5), ret); \
return ret; \
case 6: \
MRS(MAKE_##_reg(6), ret); \
return ret; \
case 7: \
MRS(MAKE_##_reg(7), ret); \
return ret; \
case 8: \
MRS(MAKE_##_reg(8), ret); \
return ret; \
case 9: \
MRS(MAKE_##_reg(9), ret); \
return ret; \
case 10: \
MRS(MAKE_##_reg(10), ret); \
return ret; \
case 11: \
MRS(MAKE_##_reg(11), ret); \
return ret; \
case 12: \
MRS(MAKE_##_reg(12), ret); \
return ret; \
case 13: \
MRS(MAKE_##_reg(13), ret); \
return ret; \
case 14: \
MRS(MAKE_##_reg(14), ret); \
return ret; \
case 15: \
MRS(MAKE_##_reg(15), ret); \
return ret; \
default: \
assert(bp_num == 0); \
MRS(MAKE_##_reg(0), ret); \
return ret; \
} \
}

/** Generates write functions for the CP14 control and value registers.
*/
#define DEBUG_GENERATE_WRITE_FN(_name, _reg) \
static inline void _name(uint16_t bp_num, word_t val) { \
switch (bp_num) { \
case 1: \
MSR(MAKE_##_reg(1), val); \
return; \
case 2: \
MSR(MAKE_##_reg(2), val); \
return; \
case 3: \
MSR(MAKE_##_reg(3), val); \
return; \
case 4: \
MSR(MAKE_##_reg(4), val); \
return; \
case 5: \
MSR(MAKE_##_reg(5), val); \
return; \
case 6: \
MSR(MAKE_##_reg(6), val); \
return; \
case 7: \
MSR(MAKE_##_reg(7), val); \
return; \
case 8: \
MSR(MAKE_##_reg(8), val); \
return; \
case 9: \
MSR(MAKE_##_reg(9), val); \
return; \
case 10: \
MSR(MAKE_##_reg(10), val); \
return; \
case 11: \
MSR(MAKE_##_reg(11), val); \
return; \
case 12: \
MSR(MAKE_##_reg(12), val); \
return; \
case 13: \
MSR(MAKE_##_reg(13), val); \
return; \
case 14: \
MSR(MAKE_##_reg(14), val); \
return; \
case 15: \
MSR(MAKE_##_reg(15), val); \
return; \
default: \
assert(bp_num == 0); \
MSR(MAKE_##_reg(0), val); \
return; \
} \
}

#endif /* ARM_BASE_CP14_SAVE_AND_RESTORE */
Loading