V7: Ad7606 serial/parallel interface

Fixed the case when it is make build without any parameter. Also updated the Copyright and Readme.md file. Signed-off-by: Ioan-daniel Pop <[email protected]>
analogdevicesinc · Feb 8, 2024 · 168e7cd · 168e7cd
1 parent ee6f65e
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diff --git a/projects/ad7606x_fmc/Makefile b/projects/ad7606x_fmc/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

diff --git a/projects/ad7606x_fmc/Readme.md b/projects/ad7606x_fmc/Readme.md
@@ -16,7 +16,12 @@ IMPORTANT: Set AD7606X device model, ADC Read Mode option and external clock opt
 
 How to use over-writable parameters from the environment:
 ```
-hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=0 SIMPLE_STATUS_CRC=0
+hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=4
 DEV_CONFIG  - Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
+INTF - Defines the operation interface: 0 - Parallel, 1 - Serial
+NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4, 8
 SIMPLE_STATUS_CRC - Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS.
 EXT_CLK - Defines the external clock option for the ADC clock: 0 - No, 1 - Yes.
+
+For the serial interface, the following parameters will be used in make command: DEV_CONFIG, INTF, NUM_OF_SDI.
+For the parallel interface, the following parameters will be used in make command: DEV_CONFIG, INTF, SIMPLE_STATUS_CRC, EXT_CLK.
diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

diff --git a/projects/ad7606x_fmc/zed/Makefile b/projects/ad7606x_fmc/zed/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

diff --git a/projects/ad7606x_fmc/zed/system_bd.tcl b/projects/ad7606x_fmc/zed/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -22,6 +22,6 @@ set EXT_CLK $ad_project_params(EXT_CLK)
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
-set sys_cstring "$DEV_CONFIG,$SIMPLE_STATUS_CRC,$EXT_CLK"
+set sys_cstring "$DEV_CONFIG,$NUM_OF_SDI,$SIMPLE_STATUS_CRC,$EXT_CLK"
 
 sysid_gen_sys_init_file $sys_cstring
diff --git a/projects/ad7606x_fmc/zed/system_constr.tcl b/projects/ad7606x_fmc/zed/system_constr.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

diff --git a/projects/ad7606x_fmc/zed/system_project.tcl b/projects/ad7606x_fmc/zed/system_project.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -11,17 +11,31 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 # DEV_CONFIG - The device which will be used
 #  - Options : AD7606B(0)/C-16(1)/C-18(2)
 # INTF - Operation interface
-#  - Options : Parallel/Serial
-# NUM_OF_SDI - NUmber of SDI lines used
+#  - Options : Parallel(0)/Serial(1)
+# NUM_OF_SDI - Number of SDI lines used
 #  - Options: 1, 2, 4, 8
 # SIMPLE_STATUS_CRC - ADC read mode options
 #  - Options : SIMPLE(0), STATUS(1), CRC(2) CRC_STATUS(3)
 # EXT_CLK - Use external clock as ADC clock
 #  - Options : No(0), Yes(1)
 
 set DEV_CONFIG [get_env_param DEV_CONFIG 0]
-set INTF [get_env_param INTF 0]
-set NUM_OF_SDI [get_env_param NUM_OF_SDI 8]
+
+# This type of check is useful when build without the INTF or NUM_OF_SDI parameters, that affect the constraints file
+set INTF 1
+if {[info exists ::env(INTF)]} {
+  set INTF $::env(INTF)
+} else {
+  set env(INTF) $INTF
+}
+
+set NUM_OF_SDI 4
+if {[info exists ::env(NUM_OF_SDI)]} {
+  set NUM_OF_SDI $::env(NUM_OF_SDI)
+} else {
+  set env(NUM_OF_SDI) $NUM_OF_SDI
+}
+
 set SIMPLE_STATUS_CRC [get_env_param SIMPLE_STATUS_CRC 0]
 set EXT_CLK [get_env_param EXT_CLK 0]
 

diff --git a/projects/ad7606x_fmc/zed/system_top_pi.v b/projects/ad7606x_fmc/zed/system_top_pi.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are

diff --git a/projects/ad7606x_fmc/zed/system_top_si.v b/projects/ad7606x_fmc/zed/system_top_si.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are