adaq42xx: Initial version of ADAQ42xx for revision w/ isolators

Signed-off-by: Liviu Adace <[email protected]>
analogdevicesinc · Nov 3, 2023 · dc2e5c3 · dc2e5c3
1 parent 4742653
commit dc2e5c3
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Showing 4 changed files with 35 additions and 4 deletions.
diff --git a/projects/ad4630_fmc/common/ad463x_adaq42xx_bd.tcl b/projects/ad4630_fmc/common/ad463x_adaq42xx_bd.tcl
@@ -22,6 +22,9 @@ set cnv_ref_clk 100
 # NOTE: this is a default value, software may or may not change this
 set adc_sampling_rate 1000000
 
+# specify the MAX17687 and LT8608 SYNC signal frequency (400KHz)
+set max17687_sync_freq 400000
+
 #create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad463x_adaq42xx_spi
 
 create_bd_port -dir O ad463x_adaq42xx_spi_sclk
@@ -30,11 +33,12 @@ create_bd_port -dir O ad463x_adaq42xx_spi_sdo
 create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_adaq42xx_spi_sdi
 
 create_bd_port -dir I ad463x_adaq42xx_echo_sclk
-
 create_bd_port -dir I ad463x_adaq42xx_busy
 create_bd_port -dir O ad463x_adaq42xx_cnv
 create_bd_port -dir I ad463x_adaq42xx_ext_clk
 
+create_bd_port -dir O max17687_sync_clk
+
 ## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
 
 ad_ip_instance axi_clkgen spi_clkgen
@@ -71,6 +75,9 @@ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3
 ## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk)
 set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]
 
+## setup the pulse period for the MAX17687 and LT8608 SYNC signal
+set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))] 
+
 ad_ip_instance axi_pwm_gen cnv_generator
 ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
 ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle
@@ -79,6 +86,11 @@ ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle
 ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1
 ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1
 
+ad_ip_instance axi_pwm_gen sync_generator
+ad_ip_parameter sync_generator CONFIG.N_PWMS 1
+ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle
+ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))]
+
 ad_ip_instance spi_axis_reorder data_reorder
 ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
 
@@ -172,15 +184,18 @@ if {$CAPTURE_ZONE == 1} {
 
 }
 ad_connect ad463x_adaq42xx_cnv cnv_generator/pwm_1
+ad_connect max17687_sync_clk sync_generator/pwm_0
 
 # clocks
 
 ad_connect $sys_cpu_clk $hier_spi_engine/clk
 ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
+ad_connect $sys_cpu_clk sync_generator/s_axi_aclk
 ad_connect spi_clk $hier_spi_engine/spi_clk
 ad_connect spi_clk data_reorder/axis_aclk
 ad_connect spi_clk axi_ad463x_adaq42xx_dma/s_axis_aclk
 ad_connect ad463x_adaq42xx_ext_clk cnv_generator/ext_clk
+ad_connect ad463x_adaq42xx_ext_clk sync_generator/ext_clk
 
 # resets
 
@@ -202,6 +217,7 @@ ad_connect  axi_ad463x_adaq42xx_dma/s_axis data_reorder/m_axis
 
 ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
 ad_cpu_interconnect 0x44b00000 cnv_generator
+ad_cpu_interconnect 0x44c00000 sync_generator
 ad_cpu_interconnect 0x44a30000 axi_ad463x_adaq42xx_dma
 ad_cpu_interconnect 0x44a70000 spi_clkgen
 

diff --git a/projects/ad4630_fmc/common/adaq42xx_fmc.txt b/projects/ad4630_fmc/common/adaq42xx_fmc.txt
@@ -18,3 +18,7 @@ H04     CLK0_M2C_P  CLK             adaq42xx_ext_clk      LVCMOS25   #N/A
 G12     LA08_P      MUX_A0          adaq42xx_pgia_mux[0]  LVCMOS25   #N/A
 G13     LA08_N      MUX_A1          adaq42xx_pgia_mux[1]  LVCMOS25   #N/A
 
+H13     LA07_P      RST             max17687_rst          LVCMOS25   #N/A
+H14     LA07_N      EN              max17687_en           LVCMOS25   #N/A
+D21     LA17_CC_N   SYNCFMC         max17687_sync_clk     LVCMOS25   #N/A
+
diff --git a/projects/ad4630_fmc/zed/system_constr_adaq42xx.xdc b/projects/ad4630_fmc/zed/system_constr_adaq42xx.xdc
@@ -17,6 +17,10 @@ set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq4
 set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports adaq42xx_pgia_mux[0]]               ; ## G12  FMC-LA08_P
 set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports adaq42xx_pgia_mux[1]]               ; ## G13  FMC-LA08_N
 
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst]                       ; ## H13  FMC-LA07_P
+set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en]                        ; ## H14  FMC-LA07_N
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk]                  ; ## D21  FMC-LA17_N_CC
+
 # external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
 create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_adaq42xx_ext_clk]
 

diff --git a/projects/ad4630_fmc/zed/system_top_adaq42xx.v b/projects/ad4630_fmc/zed/system_top_adaq42xx.v
@@ -97,7 +97,11 @@ module system_top #(
   input           ad463x_adaq42xx_busy,
   inout           ad463x_adaq42xx_resetn,
 
-  inout   [ 1:0]  adaq42xx_pgia_mux
+  inout   [ 1:0]  adaq42xx_pgia_mux,
+
+  inout           max17687_rst,
+  output          max17687_en,
+  output          max17687_sync_clk
 );
 
   // internal signals
@@ -116,7 +120,8 @@ module system_top #(
 
   // instantiations
 
-  assign gpio_i[63:35] = 29'b0;
+  assign gpio_i[63:36] = 27'b0;
+  assign max17687_en = 1'b1;
 
   ad_data_clk #(
     .SINGLE_ENDED (1)
@@ -142,7 +147,8 @@ module system_top #(
     .dio_t(gpio_t[34:32]),
     .dio_i(gpio_o[34:32]),
     .dio_o(gpio_i[34:32]),
-    .dio_p ({adaq42xx_pgia_mux,         // 34:33 
+    .dio_p ({max17687_rst,              // 35
+             adaq42xx_pgia_mux,         // 34:33 
              ad463x_adaq42xx_resetn})); // 32
 
   ad_iobuf #(
@@ -238,6 +244,7 @@ module system_top #(
     .ad463x_adaq42xx_busy (ad463x_adaq42xx_busy),
     .ad463x_adaq42xx_cnv (ad463x_adaq42xx_cnv),
     .ad463x_adaq42xx_ext_clk (ext_clk_s),
+    .max17687_sync_clk (max17687_sync_clk),
     .otg_vbusoc (otg_vbusoc),
     .spdif (spdif));