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Ad7606 serial/parallel interface #1206

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Apr 26, 2024
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Ad7606 serial/parallel interface #1206

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Ad7606 serial/parallel interface
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258 changes: 129 additions & 129 deletions library/axi_ad7606x/axi_ad7606x.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -37,142 +37,142 @@

module axi_ad7606x #(

parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_CH_DW = 16,
parameter ADC_N_BITS = 16,
parameter EXTERNAL_CLK = 0
parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_TO_DMA_N_BITS = 16,
parameter ADC_N_BITS = 16,
parameter EXTERNAL_CLK = 0
) (

// physical data interface

output rx_cs_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
input external_clk,
output rx_cs_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
input external_clk,

// physical control interface

input rx_busy,
input first_data,
input rx_busy,
input first_data,

// AXI Slave Memory Map

input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,

input adc_dovf,
output adc_clk,

output adc_valid,
output [ADC_CH_DW-1:0] adc_data_0,
output [ADC_CH_DW-1:0] adc_data_1,
output [ADC_CH_DW-1:0] adc_data_2,
output [ADC_CH_DW-1:0] adc_data_3,
output [ADC_CH_DW-1:0] adc_data_4,
output [ADC_CH_DW-1:0] adc_data_5,
output [ADC_CH_DW-1:0] adc_data_6,
output [ADC_CH_DW-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_reset
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,

input adc_dovf,
output adc_clk,

output adc_valid,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_0,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_1,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_2,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_3,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_4,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_5,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_6,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_reset
);

localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;
localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;

// internal registers

reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;

// internal signals

wire [ADC_N_BITS-1:0] adc_data_0_s;
wire [ADC_N_BITS-1:0] adc_data_1_s;
wire [ADC_N_BITS-1:0] adc_data_2_s;
wire [ADC_N_BITS-1:0] adc_data_3_s;
wire [ADC_N_BITS-1:0] adc_data_4_s;
wire [ADC_N_BITS-1:0] adc_data_5_s;
wire [ADC_N_BITS-1:0] adc_data_6_s;
wire [ADC_N_BITS-1:0] adc_data_7_s;
wire [(8*ADC_N_BITS)-1:0] adc_data_s;
wire [ 7:0] adc_status_header[0:7];
wire adc_status;
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;

wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
wire adc_dfmt_se_s[0:7];

wire adc_clk_s;
wire [ 7:0] adc_enable;
wire adc_reset_s;

wire [(8*ADC_CH_DW)-1:0] dma_data;
wire dma_dvalid;

wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;

wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;

wire [31:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [31:0] adc_config_ctrl_s;
wire adc_ctrl_status_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
wire [ADC_N_BITS-1:0] adc_data_0_s;
wire [ADC_N_BITS-1:0] adc_data_1_s;
wire [ADC_N_BITS-1:0] adc_data_2_s;
wire [ADC_N_BITS-1:0] adc_data_3_s;
wire [ADC_N_BITS-1:0] adc_data_4_s;
wire [ADC_N_BITS-1:0] adc_data_5_s;
wire [ADC_N_BITS-1:0] adc_data_6_s;
wire [ADC_N_BITS-1:0] adc_data_7_s;
wire [(8*ADC_N_BITS)-1:0] adc_data_s;
wire [ 7:0] adc_status_header[0:7];
wire adc_status;
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;

wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
wire adc_dfmt_se_s[0:7];

wire adc_clk_s;
wire [ 7:0] adc_enable;
wire adc_reset_s;

wire [(8*ADC_TO_DMA_N_BITS)-1:0] dma_data;
wire dma_dvalid;

wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;

wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;

wire [31:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [31:0] adc_config_ctrl_s;
wire adc_ctrl_status_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;

// defaults

Expand Down Expand Up @@ -287,13 +287,13 @@ module axi_ad7606x #(
for (k = 0;k < 8;k = k + 1) begin
ad_datafmt #(
.DATA_WIDTH (ADC_N_BITS),
.BITS_PER_SAMPLE (ADC_CH_DW)
.BITS_PER_SAMPLE (ADC_TO_DMA_N_BITS)
) i_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]),
.valid_out (dma_dvalid),
.data_out (dma_data[k*ADC_CH_DW+(ADC_CH_DW-1):k*ADC_CH_DW]),
.data_out (dma_data[k*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):k*ADC_TO_DMA_N_BITS]),
.dfmt_enable (adc_dfmt_enable_s[k]),
.dfmt_type (adc_dfmt_type_s[k]),
.dfmt_se (adc_dfmt_se_s[k]));
Expand Down Expand Up @@ -385,14 +385,14 @@ module axi_ad7606x #(
endgenerate

assign adc_data_s = {adc_data_0_s,adc_data_1_s,adc_data_2_s,adc_data_3_s,adc_data_4_s,adc_data_5_s,adc_data_6_s,adc_data_7_s};
assign adc_data_7 = dma_data[0*ADC_CH_DW+(ADC_CH_DW-1):0*ADC_CH_DW];
assign adc_data_6 = dma_data[1*ADC_CH_DW+(ADC_CH_DW-1):1*ADC_CH_DW];
assign adc_data_5 = dma_data[2*ADC_CH_DW+(ADC_CH_DW-1):2*ADC_CH_DW];
assign adc_data_4 = dma_data[3*ADC_CH_DW+(ADC_CH_DW-1):3*ADC_CH_DW];
assign adc_data_3 = dma_data[4*ADC_CH_DW+(ADC_CH_DW-1):4*ADC_CH_DW];
assign adc_data_2 = dma_data[5*ADC_CH_DW+(ADC_CH_DW-1):5*ADC_CH_DW];
assign adc_data_1 = dma_data[6*ADC_CH_DW+(ADC_CH_DW-1):6*ADC_CH_DW];
assign adc_data_0 = dma_data[7*ADC_CH_DW+(ADC_CH_DW-1):7*ADC_CH_DW];
assign adc_data_7 = dma_data[0*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):0*ADC_TO_DMA_N_BITS];
assign adc_data_6 = dma_data[1*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):1*ADC_TO_DMA_N_BITS];
assign adc_data_5 = dma_data[2*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):2*ADC_TO_DMA_N_BITS];
assign adc_data_4 = dma_data[3*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):3*ADC_TO_DMA_N_BITS];
assign adc_data_3 = dma_data[4*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):4*ADC_TO_DMA_N_BITS];
assign adc_data_2 = dma_data[5*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):5*ADC_TO_DMA_N_BITS];
assign adc_data_1 = dma_data[6*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):6*ADC_TO_DMA_N_BITS];
assign adc_data_0 = dma_data[7*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):7*ADC_TO_DMA_N_BITS];

up_adc_common #(
.ID (ID),
Expand Down
29 changes: 23 additions & 6 deletions projects/ad7606x_fmc/Readme.md
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Please add more details regarding the valid combinations of build parameters. you can use this readme as reference
https://github.com/analogdevicesinc/hdl/blob/main/projects/ad4630_fmc/zed/README.md

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Done.

Original file line number Diff line number Diff line change
Expand Up @@ -3,20 +3,37 @@
Here are some pointers to help you:
* [EVAL-AD7606B Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7606b-fmcz.html)
* [EVAL-AD7606C-16/18 Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7606c-18.html)
* Parts : AD7606B [8 Channels, 16-bit, 800 kSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606b.html)
* Parts : AD7606C-16 [8 Channels, 16-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-16.html)
* Parts : AD7606B [8 Channels, 18-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-18.html)
* Parts : [AD7606B, 8 Channels, 16-bit, 800 kSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606b.html)
* Parts : [AD7606B, 8 Channels, 18-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-18.html)
* Parts : [AD7606C-16, 8 Channels, 16-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-16.html)
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmcz
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl
* NO-OS Drivers: [AD7606 - No-OS Driver](https://wiki.analog.com/resources/tools-software/uc-drivers/ad7606)
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl
## Building, Generating Bit Files
## Building, Generating Bit Files

IMPORTANT: Set AD7606X device model, ADC Read Mode option and external clock option

How to use over-writable parameters from the environment:
```
hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=0 SIMPLE_STATUS_CRC=0
hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=4
DEV_CONFIG - Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
SIMPLE_STATUS_CRC - Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS.
INTF - Defines the operation interface: 0 - Parallel, 1 - Serial
NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4, 8
EXT_CLK - Defines the external clock option for the ADC clock: 0 - No, 1 - Yes.

For the serial interface, the following parameters will be used in make command: DEV_CONFIG, INTF, NUM_OF_SDI.
For the parallel interface, the following parameters will be used in make command: DEV_CONFIG, INTF,EXT_CLK.

**Example:**

make DEV_CONFIG=0 INTF=1 NUM_OF_SDI=1
make DEV_CONFIG=1 INTF=1 NUM_OF_SDI=2
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=1
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=2
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=4
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=8
make DEV_CONFIG=0 INTF=0 EXT_CLK=0
make DEV_CONFIG=1 INTF=0 EXT_CLK=0
make DEV_CONFIG=2 INTF=0 EXT_CLK=0
...
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