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Dev #21

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Dev #21

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2 changes: 1 addition & 1 deletion arch/arm/dts/sc58x.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@
};

&mmc{
clocks = <&dummy>, <&clk ADSP_SC58X_CLK_CGU0_SCLK0>;
clocks = <&clk ADSP_SC58X_CLK_CGU0_SCLK0>, <&clk ADSP_SC58X_CLK_SDIO>;
};

&i2c0{
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14 changes: 8 additions & 6 deletions arch/arm/mach-sc5xx/init/dmc/dmcinit.c
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* (C) Copyright 2022 - Analog Devices, Inc.
* (C) Copyright 2022-2024 - Analog Devices, Inc.
*
* Written and/or maintained by Timesys Corporation
*
Expand Down Expand Up @@ -327,6 +327,13 @@ __attribute__((always_inline)) static inline void dmc_controller_init(void)
#ifndef CONFIG_SC59X
writel(dmc.dmc_data_calib_add_value, dmc.reg->REG_DMC_DT_CALIB_ADDR);
#endif

#if defined(CONFIG_SC57X) || defined(CONFIG_SC58X)
// SC58xx and SC57xx programming DMC_DLLCTL.DLLCALRDCNT should be done before DMC Initialisaiton
/* Program the DMCx_CTL.DLLCTL register with 0x948 value
* (DATACYC=9, DLLCALRDCNT=72). */
writel(0x00000948, dmc.reg->REG_DMC_DLLCTL);
#endif
/* 3. Program the DMCx_CTL register with INIT bit set to start
* the DMC initialization sequence */
writel(dmc.dmc_ctl_value, dmc.reg->REG_DMC_CTL);
Expand Down Expand Up @@ -461,11 +468,6 @@ __attribute__((always_inline)) static inline void dmc_controller_init(void)
}
dmcdelay(2500u);
#endif

#else
/* 5. Program the DMCx_CTL.DLLCTL register with 0x948 value
* (DATACYC=9, DLLCALRDCNT=72). */
writel(0x00000948, dmc.reg->REG_DMC_DLLCTL);
#endif

/* 6. Workaround for anomaly#20000037 */
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1 change: 0 additions & 1 deletion configs/sc594-som-ezkit-spl_defconfig
Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,6 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
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