spi_engine: update for hdl 1.4.0

Signed-off-by: Laez Barbosa <[email protected]>
analogdevicesinc · Jan 30, 2025 · 673b70a · 673b70a
1 parent bb7e91b
commit 673b70a
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Showing 15 changed files with 991 additions and 29 deletions.
diff --git a/library/regmaps/adi_regmap_spi_engine_pkg.sv b/library/regmaps/adi_regmap_spi_engine_pkg.sv
@@ -33,7 +33,7 @@
 // ***************************************************************************
 // ***************************************************************************
 /* Auto generated Register Map */
-/* Wed Jul 24 09:28:37 2024 */
+/* Wed Jan 29 16:40:28 2025 */
 
 package adi_regmap_spi_engine_pkg;
   import adi_regmap_pkg::*;
@@ -43,8 +43,8 @@ package adi_regmap_spi_engine_pkg;
 
   const reg_t AXI_SPI_ENGINE_VERSION = '{ 'h0000, "VERSION" , '{
     "VERSION_MAJOR": '{ 31, 16, RO, 'h00000001 },
-    "VERSION_MINOR": '{ 15, 8, RO, 'h00000003 },
-    "VERSION_PATCH": '{ 7, 0, RO, 'h00000001 }}};
+    "VERSION_MINOR": '{ 15, 8, RO, 'h00000004 },
+    "VERSION_PATCH": '{ 7, 0, RO, 'h00000000 }}};
   `define SET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) SetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
   `define GET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) GetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
   `define DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR GetResetValue(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR")
@@ -167,7 +167,7 @@ package adi_regmap_spi_engine_pkg;
   `define UPDATE_AXI_SPI_ENGINE_IRQ_SOURCE_IRQ_SOURCE(x,y) UpdateField(AXI_SPI_ENGINE_IRQ_SOURCE,"IRQ_SOURCE",x,y)
 
   const reg_t AXI_SPI_ENGINE_SYNC_ID = '{ 'h00c0, "SYNC_ID" , '{
-    "SYNC_ID": '{ 31, 0, RO, 'hXXXXXXXX }}};
+    "SYNC_ID": '{ 31, 0, RO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID(x) SetField(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID",x)
   `define GET_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID(x) GetField(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID",x)
   `define DEFAULT_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID GetResetValue(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID")
@@ -202,35 +202,35 @@ package adi_regmap_spi_engine_pkg;
   `define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_LEVEL_SDI_FIFO_LEVEL(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO_LEVEL,"SDI_FIFO_LEVEL",x,y)
 
   const reg_t AXI_SPI_ENGINE_CMD_FIFO = '{ 'h00e0, "CMD_FIFO" , '{
-    "CMD_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
+    "CMD_FIFO": '{ 31, 0, WO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO(x) SetField(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO",x)
   `define GET_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO(x) GetField(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO",x)
   `define DEFAULT_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO GetResetValue(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO")
   `define UPDATE_AXI_SPI_ENGINE_CMD_FIFO_CMD_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_CMD_FIFO,"CMD_FIFO",x,y)
 
   const reg_t AXI_SPI_ENGINE_SDO_FIFO = '{ 'h00e4, "SDO_FIFO" , '{
-    "SDO_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
+    "SDO_FIFO": '{ 31, 0, WO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(x) SetField(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO",x)
   `define GET_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(x) GetField(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO",x)
   `define DEFAULT_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO GetResetValue(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO")
   `define UPDATE_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_SDO_FIFO,"SDO_FIFO",x,y)
 
   const reg_t AXI_SPI_ENGINE_SDI_FIFO = '{ 'h00e8, "SDI_FIFO" , '{
-    "SDI_FIFO": '{ 31, 0, RO, 'hXXXXXXXX }}};
+    "SDI_FIFO": '{ 31, 0, RO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(x) SetField(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO",x)
   `define GET_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(x) GetField(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO",x)
   `define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO GetResetValue(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO")
   `define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO,"SDI_FIFO",x,y)
 
   const reg_t AXI_SPI_ENGINE_SDI_FIFO_MSB = '{ 'h00ec, "SDI_FIFO_MSB" , '{
-    "SDI_FIFO_MSB": '{ 31, 0, RO, 'hXXXXXXXX }}};
+    "SDI_FIFO_MSB": '{ 31, 0, RO, 0 }}};
   `define SET_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB(x) SetField(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB",x)
   `define GET_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB(x) GetField(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB",x)
   `define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB GetResetValue(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB")
   `define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_MSB_SDI_FIFO_MSB(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO_MSB,"SDI_FIFO_MSB",x,y)
 
   const reg_t AXI_SPI_ENGINE_SDI_FIFO_PEEK = '{ 'h00f0, "SDI_FIFO_PEEK" , '{
-    "SDI_FIFO_PEEK": '{ 31, 0, RO, 'hXXXXXXXX }}};
+    "SDI_FIFO_PEEK": '{ 31, 0, RO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK(x) SetField(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK",x)
   `define GET_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK(x) GetField(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK",x)
   `define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK GetResetValue(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK")
@@ -258,14 +258,14 @@ package adi_regmap_spi_engine_pkg;
   `define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET",x,y)
 
   const reg_t AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO = '{ 'h0110, "OFFLOAD0_CDM_FIFO" , '{
-    "OFFLOAD0_CDM_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
+    "OFFLOAD0_CDM_FIFO": '{ 31, 0, WO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x)
   `define GET_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x)
   `define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO")
   `define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x,y)
 
   const reg_t AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO = '{ 'h0114, "OFFLOAD0_SDO_FIFO" , '{
-    "OFFLOAD0_SDO_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
+    "OFFLOAD0_SDO_FIFO": '{ 31, 0, WO, 'h00 }}};
   `define SET_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO,"OFFLOAD0_SDO_FIFO",x)
   `define GET_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO,"OFFLOAD0_SDO_FIFO",x)
   `define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO,"OFFLOAD0_SDO_FIFO")

diff --git a/testbenches/ip/spi_engine/cfgs/cfg00.tcl b/testbenches/ip/spi_engine/cfgs/cfg00.tcl
@@ -0,0 +1,58 @@
+global ad_project_params
+
+# SPI Engine DUT parameters
+set ad_project_params(DATA_WIDTH)           32
+set ad_project_params(ASYNC_SPI_CLK)        1
+set ad_project_params(NUM_OF_CS)            1
+set ad_project_params(NUM_OF_SDI)           1
+set ad_project_params(NUM_OF_SDO)           1
+set ad_project_params(SDI_DELAY)            1
+set ad_project_params(ECHO_SCLK)            0
+set ad_project_params(CMD_MEM_ADDR_WIDTH)   4
+set ad_project_params(DATA_MEM_ADDR_WIDTH)  4
+set ad_project_params(SDI_FIFO_ADDR_WIDTH)  5
+set ad_project_params(SDO_FIFO_ADDR_WIDTH)  5
+set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
+set ad_project_params(CMD_FIFO_ADDR_WIDTH)  4
+set ad_project_params(SDO_STREAMING)        0
+
+# Test parameters
+set ad_project_params(DATA_DLENGTH)         16
+set ad_project_params(THREE_WIRE)           0
+set ad_project_params(CPOL)                 0
+set ad_project_params(CPHA)                 0
+set ad_project_params(SDO_IDLE_STATE)       0
+set ad_project_params(SLAVE_TIN)            0
+set ad_project_params(SLAVE_TOUT)           0
+set ad_project_params(MASTER_TIN)           0
+set ad_project_params(MASTER_TOUT)          0
+set ad_project_params(CS_TO_MISO)           0
+set ad_project_params(CLOCK_DIVIDER)        2
+set ad_project_params(NUM_OF_WORDS)         5
+set ad_project_params(NUM_OF_TRANSFERS)     5
+set ad_project_params(CS_ACTIVE_HIGH)       0
+set ad_project_params(ECHO_SCLK_DELAY)      0.1
+
+set spi_s_vip_cfg [ list \
+    MODE            0                                   \
+    CPOL            $ad_project_params(CPOL)            \
+    CPHA            $ad_project_params(CPHA)            \
+    INV_CS          $ad_project_params(CS_ACTIVE_HIGH)  \
+    SLAVE_TIN       $ad_project_params(SLAVE_TIN)       \
+    SLAVE_TOUT      $ad_project_params(SLAVE_TOUT)      \
+    MASTER_TIN      $ad_project_params(MASTER_TIN)      \
+    MASTER_TOUT     $ad_project_params(MASTER_TOUT)     \
+    CS_TO_MISO      $ad_project_params(CS_TO_MISO)      \
+    DATA_DLENGTH    $ad_project_params(DATA_DLENGTH)    \
+]
+set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
+
+set axis_sdo_src_vip_cfg [ list \
+    INTERFACE_MODE {MASTER} \
+    HAS_TREADY 1 \
+    HAS_TLAST 0 \
+    TDATA_NUM_BYTES [expr  $ad_project_params(DATA_WIDTH)/8] \
+    TDEST_WIDTH 0 \
+    TID_WIDTH 0 \
+]
+set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
diff --git a/testbenches/ip/spi_engine/cfgs/cfg1.tcl → testbenches/ip/spi_engine/cfgs/cfg01.tcl b/testbenches/ip/spi_engine/cfgs/cfg1.tcl → testbenches/ip/spi_engine/cfgs/cfg01.tcl
@@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS)         3
 set ad_project_params(NUM_OF_TRANSFERS)     5
 set ad_project_params(CS_ACTIVE_HIGH)       0
 set ad_project_params(ECHO_SCLK_DELAY)      0.1
-set ad_project_params(SDO_MEM_WORDS)        1
 
 set spi_s_vip_cfg [ list \
     MODE            0                                   \

diff --git a/testbenches/ip/spi_engine/cfgs/cfg10.tcl b/testbenches/ip/spi_engine/cfgs/cfg10.tcl
@@ -0,0 +1,58 @@
+global ad_project_params
+
+# SPI Engine DUT parameters
+set ad_project_params(DATA_WIDTH)           32
+set ad_project_params(ASYNC_SPI_CLK)        1
+set ad_project_params(NUM_OF_CS)            1
+set ad_project_params(NUM_OF_SDI)           1
+set ad_project_params(NUM_OF_SDO)           1
+set ad_project_params(SDI_DELAY)            1
+set ad_project_params(ECHO_SCLK)            0
+set ad_project_params(CMD_MEM_ADDR_WIDTH)   4
+set ad_project_params(DATA_MEM_ADDR_WIDTH)  4
+set ad_project_params(SDI_FIFO_ADDR_WIDTH)  5
+set ad_project_params(SDO_FIFO_ADDR_WIDTH)  5
+set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
+set ad_project_params(CMD_FIFO_ADDR_WIDTH)  4
+set ad_project_params(SDO_STREAMING)        0
+
+# Test parameters
+set ad_project_params(DATA_DLENGTH)         18
+set ad_project_params(THREE_WIRE)           0
+set ad_project_params(CPOL)                 1
+set ad_project_params(CPHA)                 0
+set ad_project_params(SDO_IDLE_STATE)       0
+set ad_project_params(SLAVE_TIN)            0
+set ad_project_params(SLAVE_TOUT)           0
+set ad_project_params(MASTER_TIN)           0
+set ad_project_params(MASTER_TOUT)          0
+set ad_project_params(CS_TO_MISO)           0
+set ad_project_params(CLOCK_DIVIDER)        2
+set ad_project_params(NUM_OF_WORDS)         3
+set ad_project_params(NUM_OF_TRANSFERS)     5
+set ad_project_params(CS_ACTIVE_HIGH)       0
+set ad_project_params(ECHO_SCLK_DELAY)      0.1
+
+set spi_s_vip_cfg [ list \
+    MODE            0                                   \
+    CPOL            $ad_project_params(CPOL)            \
+    CPHA            $ad_project_params(CPHA)            \
+    INV_CS          $ad_project_params(CS_ACTIVE_HIGH)  \
+    SLAVE_TIN       $ad_project_params(SLAVE_TIN)       \
+    SLAVE_TOUT      $ad_project_params(SLAVE_TOUT)      \
+    MASTER_TIN      $ad_project_params(MASTER_TIN)      \
+    MASTER_TOUT     $ad_project_params(MASTER_TOUT)     \
+    CS_TO_MISO      $ad_project_params(CS_TO_MISO)      \
+    DATA_DLENGTH    $ad_project_params(DATA_DLENGTH)    \
+]
+set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
+
+set axis_sdo_src_vip_cfg [ list \
+    INTERFACE_MODE {MASTER} \
+    HAS_TREADY 1 \
+    HAS_TLAST 0 \
+    TDATA_NUM_BYTES [expr  $ad_project_params(DATA_WIDTH)/8] \
+    TDEST_WIDTH 0 \
+    TID_WIDTH 0 \
+]
+set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
diff --git a/testbenches/ip/spi_engine/cfgs/cfg11.tcl b/testbenches/ip/spi_engine/cfgs/cfg11.tcl
@@ -0,0 +1,58 @@
+global ad_project_params
+
+# SPI Engine DUT parameters
+set ad_project_params(DATA_WIDTH)           32
+set ad_project_params(ASYNC_SPI_CLK)        1
+set ad_project_params(NUM_OF_CS)            1
+set ad_project_params(NUM_OF_SDI)           1
+set ad_project_params(NUM_OF_SDO)           1
+set ad_project_params(SDI_DELAY)            1
+set ad_project_params(ECHO_SCLK)            0
+set ad_project_params(CMD_MEM_ADDR_WIDTH)   4
+set ad_project_params(DATA_MEM_ADDR_WIDTH)  4
+set ad_project_params(SDI_FIFO_ADDR_WIDTH)  5
+set ad_project_params(SDO_FIFO_ADDR_WIDTH)  5
+set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
+set ad_project_params(CMD_FIFO_ADDR_WIDTH)  4
+set ad_project_params(SDO_STREAMING)        0
+
+# Test parameters
+set ad_project_params(DATA_DLENGTH)         18
+set ad_project_params(THREE_WIRE)           0
+set ad_project_params(CPOL)                 1
+set ad_project_params(CPHA)                 1
+set ad_project_params(SDO_IDLE_STATE)       0
+set ad_project_params(SLAVE_TIN)            0
+set ad_project_params(SLAVE_TOUT)           0
+set ad_project_params(MASTER_TIN)           0
+set ad_project_params(MASTER_TOUT)          0
+set ad_project_params(CS_TO_MISO)           0
+set ad_project_params(CLOCK_DIVIDER)        2
+set ad_project_params(NUM_OF_WORDS)         3
+set ad_project_params(NUM_OF_TRANSFERS)     5
+set ad_project_params(CS_ACTIVE_HIGH)       0
+set ad_project_params(ECHO_SCLK_DELAY)      0.1
+
+set spi_s_vip_cfg [ list \
+    MODE            0                                   \
+    CPOL            $ad_project_params(CPOL)            \
+    CPHA            $ad_project_params(CPHA)            \
+    INV_CS          $ad_project_params(CS_ACTIVE_HIGH)  \
+    SLAVE_TIN       $ad_project_params(SLAVE_TIN)       \
+    SLAVE_TOUT      $ad_project_params(SLAVE_TOUT)      \
+    MASTER_TIN      $ad_project_params(MASTER_TIN)      \
+    MASTER_TOUT     $ad_project_params(MASTER_TOUT)     \
+    CS_TO_MISO      $ad_project_params(CS_TO_MISO)      \
+    DATA_DLENGTH    $ad_project_params(DATA_DLENGTH)    \
+]
+set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
+
+set axis_sdo_src_vip_cfg [ list \
+    INTERFACE_MODE {MASTER} \
+    HAS_TREADY 1 \
+    HAS_TLAST 0 \
+    TDATA_NUM_BYTES [expr  $ad_project_params(DATA_WIDTH)/8] \
+    TDEST_WIDTH 0 \
+    TID_WIDTH 0 \
+]
+set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
diff --git a/testbenches/ip/spi_engine/cfgs/cfg_inv_cs.tcl b/testbenches/ip/spi_engine/cfgs/cfg_inv_cs.tcl
@@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS)         3
 set ad_project_params(NUM_OF_TRANSFERS)     5
 set ad_project_params(CS_ACTIVE_HIGH)       1
 set ad_project_params(ECHO_SCLK_DELAY)      0.1
-set ad_project_params(SDO_MEM_WORDS)        2
 
 set spi_s_vip_cfg [ list \
     MODE            0                                   \

diff --git a/testbenches/ip/spi_engine/cfgs/cfg_sdo_streaming.tcl b/testbenches/ip/spi_engine/cfgs/cfg_sdo_streaming.tcl
@@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS)         5
 set ad_project_params(NUM_OF_TRANSFERS)     3
 set ad_project_params(CS_ACTIVE_HIGH)       0
 set ad_project_params(ECHO_SCLK_DELAY)      0.1
-set ad_project_params(SDO_MEM_WORDS)        2
 
 set spi_s_vip_cfg [ list \
     MODE            0                                   \

diff --git a/testbenches/ip/spi_engine/system_project.tcl b/testbenches/ip/spi_engine/system_project.tcl
@@ -27,6 +27,7 @@ adi_sim_project_files [list \
  "spi_environment.sv" \
  "tests/test_program.sv" \
  "tests/test_sleep_delay.sv" \
+ "tests/test_slowdata.sv" \
  ]
 
 #set a default test program

diff --git a/testbenches/ip/spi_engine/tests/test_program.sv b/testbenches/ip/spi_engine/tests/test_program.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -274,8 +274,6 @@ bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)
 bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0];
 bit [`DATA_DLENGTH-1:0] rx_data;
 bit [`DATA_DLENGTH-1:0] tx_data;
-localparam sdo_mem_num = (`SDO_STREAMING) ? (`MIN((`NUM_OF_WORDS),(`SDO_MEM_WORDS))) : (`NUM_OF_WORDS);
-bit [`DATA_DLENGTH-1:0] one_shot_sdo_data [sdo_mem_num-1 :0] = '{default:'0};
 
 task offload_spi_test();
   //Configure DMA
@@ -301,21 +299,21 @@ task offload_spi_test();
   axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2);
 
   // Enqueue transfers transfers to DUT
-  for (int i = 0; i<sdo_mem_num; i=i+1) begin
-    one_shot_sdo_data[i] = $urandom;
-    axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), one_shot_sdo_data[i]);
-  end
   for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin
     rx_data = $urandom;
     spi_send(rx_data);
-    sdi_read_data_store[i]  = rx_data;
-    if (i%(`NUM_OF_WORDS)<sdo_mem_num) begin
-      tx_data = one_shot_sdo_data[i%(`NUM_OF_WORDS)];
-    end else begin
-      tx_data = $urandom;
+    sdi_read_data_store[i]  = rx_data; tx_data = $urandom;
+  `ifdef DEF_SDO_STREAMING
       sdo_stream_gen(tx_data);
-    end
-    sdo_write_data_store[i] = tx_data;
+      sdo_write_data_store[i] = tx_data;
+  `else
+      if (i<(`NUM_OF_WORDS)) begin
+        sdo_write_data_store[i] = tx_data;
+        axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]);
+      end else begin
+        sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)];
+      end
+  `endif
   end
 
   // Start the offload