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Util axis fifo asym tb#77

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IstvanZsSzekely wants to merge 17 commits intomainanalogdevicesinc/testbenches:mainfrom util_axis_fifo_asym_tbanalogdevicesinc/testbenches:util_axis_fifo_asym_tbCopy head branch name to clipboard

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Commits on Jan 20, 2025

• infrastructure refactorization

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• infrastructure refactorization: Fixes

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• infrastructure refactorization: Refactoring

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• infrastructure refactorization: Generalized scoreboard

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• infrastructure refactorization: Updated DMA loopback project

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• infrastructure refactorization: Fixed address value in DMA loopback for DDR

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• infrastructure refactorization: Updated IP level testbenches

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• infrastructure refactorization: IP level updates

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• infrastructure refactorization: Updated Project level testbenches

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• infrastructure refactorization: Updates and fixes

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• ad7616: Fixes

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• dma_flock: Fixed testbench after rebase

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Commits on Jan 21, 2025

• adi_datatypes: Added FIFO and LIFO class implementation

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• util_axis_fifo_asym: Initial testbench commit

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Commits on Jan 22, 2025

• util_axis_fifo_asym: Updated after rebase

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• util_axis_fifo_asym: Updates and fixes

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• util_axis_fifo_asym: Updated waveform configuration

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