Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

valentyusb serial #347

Draft
wants to merge 4 commits into
base: master
Choose a base branch
from
Draft

valentyusb serial #347

wants to merge 4 commits into from

Commits on Mar 4, 2022

  1. Makefile: depend on soc_extra_v 

    Signed-off-by: Matt Johnston <[email protected]>
    @mkj
    mkj committed Mar 4, 2022
    Configuration menu
    Copy the full SHA
    f57e206 View commit details
    Browse the repository at this point in the history

  2. valentyusb: Add USB UART to SOC and OrangeCrab 

    An extra uart is added at 0xc0008000 attached to valentyusb, using
the OrangeCrab's onboard USB port.
This has a liteuart interface, an identifier bit is added to syscon.

Generated from branch hw_cdc_eptri of
https://github.com/litex-hub/valentyusb

The generate script is based on valentyusb/sim/generate_verilog.py

UARTUSB: usbserial@8000 {
        device_type = "serial";
        compatible = "litex,liteuart";
        reg = <0x8000 0x100>;
        interrupts = <0x15 0x1>;
};

(requires extra kernel patches for early console at present v5.16)

Signed-off-by: Matt Johnston <[email protected]>
    @mkj
    mkj committed Mar 4, 2022
    Configuration menu
    Copy the full SHA
    6be3e1a View commit details
    Browse the repository at this point in the history

  3. valentyusb: Add software for liteuart console 

    usb_hello is a copy of hello_world but uses both consoles

Signed-off-by: Matt Johnston <[email protected]>
    @mkj
    mkj committed Mar 4, 2022
    Configuration menu
    Copy the full SHA
    7f9f848 View commit details
    Browse the repository at this point in the history

  4. Makefile: Don't force generic USE_LITEDRAM=true 

    That makes it easier to override a non-litedram build for testing
RAM_INIT_FILE, eg

make microwatt.dfu  LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=false  RAM_INIT_FILE=usb_hello/usb_hello.hex

Signed-off-by: Matt Johnston <[email protected]>
    @mkj
    mkj committed Mar 4, 2022
    Configuration menu
    Copy the full SHA
    9cb4948 View commit details
    Browse the repository at this point in the history