final

design/blk_buffer.v

@@ -1,33 +1,44 @@
 module blk_buffer #(
    parameter HP = 1920,
+   parameter ML = 192,
    parameter KH = 10,
    parameter MAX = 2
 ) (
    input clk_i,
-   input freeze_i,
+   input vp_last_i,
    input hs_i,
+   input hs_r_i,
    input de_i,
+   input de_r_i,
    input [7:0] wd_i,
    output reg rx_o
 );
-   localparam BLKS = HP / KH;
+   localparam BLKS = (HP + KH - 1) / KH;
    localparam DEPTH = $clog2(MAX) + 1;
+   localparam BD = $clog2(BLKS) + 1;
+   localparam MD = $clog2(ML) + 1;
 
-   reg hs_r, de_r;
-   reg [31:0] h_cur, hb_cur;
+   reg [MD-1:0] ml_cnt;
    always @(posedge clk_i) begin
-      hs_r <= hs_i;
-      de_r <= de_i;
-      if (~de_i && de_r) begin
+      if (hs_i && ~hs_r_i) begin
+         ml_cnt <= ML - 1;
+      end else if (~de_i && de_r_i) begin
+         ml_cnt <= 0;
+      end else if (|ml_cnt) begin
+         ml_cnt <= ml_cnt - 1;
+      end
+   end
+
+   reg [BD-1:0] h_cur, hb_cur;
+   always @(posedge clk_i) begin
+      if (|ml_cnt) begin
          h_cur <= 0;
          hb_cur <= 0;
-      end else if (de_i) begin
-         if (h_cur == KH-1) begin
-            h_cur <= 0;
-            hb_cur <= hb_cur + 1;
-         end else begin
-            h_cur <= h_cur + 1;
-         end
+      end else if (h_cur == KH-1) begin
+         h_cur <= 0;
+         hb_cur <= hb_cur + 1;
+      end else begin
+         h_cur <= h_cur + 1;
       end
    end
 
@@ -39,7 +50,7 @@ module blk_buffer #(
             .DEPTH (DEPTH)
          ) i_double_buffer (
             .clk_i,
-            .freeze_i (freeze_i && hs_i && ~hs_r),
+            .freeze_i (vp_last_i && ~de_i && de_r_i),
             .de_i (de_i && i == hb_cur),
             .wd_i,
             .buf_a (buf_a[i])

design/frm_buffer.v

@@ -3,23 +3,19 @@ module frm_buffer #(
 ) (
    input clk_i,
    input vs_i,
+   input vs_r_i,
    input de_i,
    input [7:0] wd_i,
    output reg rx_o
 );
    localparam DEPTH = $clog2(MAX) + 1;
 
-   reg vs_r;
-   always @(posedge clk_i) begin
-      vs_r <= vs_i;
-   end
-
    wire [DEPTH-1:0] buf_a;
    double_buffer #(
       .DEPTH (DEPTH)
    ) i_double_buffer (
       .clk_i,
-      .freeze_i (~vs_i && vs_r),
+      .freeze_i (~vs_i && vs_r_i),
       .de_i,
       .wd_i,
       .buf_a (buf_a)

design/ip/i2c_master/i2c_config.v

@@ -64,7 +64,7 @@ wire[7:0] i2c_write_data;
 wire[7:0] i2c_read_data;
 
 wire err;
-(* MARK_DEBUG="true" *)reg[2:0] state;
+reg[2:0] state;
 
 localparam S_IDLE                =  0;
 localparam S_WR_I2C_CHECK        =  1;
@@ -155,4 +155,4 @@ i2c_master_top i2c_master_top_m0
 	.i2c_read_data(i2c_read_data),
 	.error(err)
 );
-endmodule
+endmodule

design/lin_buffer.v

@@ -2,25 +2,20 @@ module lin_buffer #(
    parameter MAX = 2
 ) (
    input clk_i,
-   input freeze_i,
-   input hs_i,
+   input vp_last_i,
    input de_i,
+   input de_r_i,
    input [7:0] wd_i,
    output reg rx_o
 );
    localparam DEPTH = $clog2(MAX) + 1;
 
-   reg hs_r;
-   always @(posedge clk_i) begin
-      hs_r <= hs_i;
-   end
-
    wire [DEPTH-1:0] buf_a;
    double_buffer #(
       .DEPTH (DEPTH)
    ) i_double_buffer (
       .clk_i,
-      .freeze_i (freeze_i && hs_i && ~hs_r),
+      .freeze_i (vp_last_i && ~de_i && de_r_i),
       .de_i,
       .wd_i,
       .buf_a (buf_a)

design/top.v

@@ -83,6 +83,14 @@ module top #(
       vin_data <= vin_data_i;
    end
 
+   // Edge detection
+   reg vin_vs_r, vin_hs_r, vin_de_r;
+   always @(posedge vin_clk_i) begin
+      vin_vs_r <= vin_vs;
+      vin_hs_r <= vin_hs;
+      vin_de_r <= vin_de;
+   end
+
    // Gray calculation
    wire [7:0] gray;
    rgb_to_gray i_rgb_to_gray (
@@ -94,31 +102,30 @@ module top #(
    );
 
    // Vertical cursor
-   reg vin_de_r;
    reg [31:0] vp_cur;
+   wire vp_last = vp_cur == KV-1;
    always @(posedge vin_clk_i) begin
       if (vin_vs) begin
          vp_cur <= 0;
-         vin_de_r <= 0;
-      end else begin
-         vin_de_r <= vin_de;
-         if (~vin_de && vin_de_r) begin
-            vp_cur <= (vp_cur == KV-1) ? 0 : vp_cur + 1;
-         end
+      end else if (~vin_de && vin_de_r) begin
+         vp_cur <= vp_last ? 0 : vp_cur + 1;
       end
    end
 
    // Blk mode
    wire blk_x;
    blk_buffer #(
       .HP (HP),
+      .ML (ML),
       .KH (KH),
       .MAX (KH * KV * 255)
    ) i_blk_buffer (
       .clk_i (vin_clk_i),
-      .freeze_i (vp_cur == KV-1),
+      .vp_last_i (vp_last),
       .hs_i (vin_hs),
+      .hs_r_i (vin_hs_r),
       .de_i (vin_de),
+      .de_r_i (vin_de_r),
       .wd_i (gray),
       .rx_o (blk_x)
    );
@@ -129,9 +136,9 @@ module top #(
       .MAX (HP * KV * 255)
    ) i_lin_buffer (
       .clk_i (vin_clk_i),
-      .freeze_i (vp_cur == KV-1),
-      .hs_i (vin_hs),
+      .vp_last_i (vp_last),
       .de_i (vin_de),
+      .de_r_i (vin_de_r),
       .wd_i (gray),
       .rx_o (lin_x)
    );
@@ -143,6 +150,7 @@ module top #(
    ) i_frm_buffer (
       .clk_i (vin_clk_i),
       .vs_i (vin_vs),
+      .vs_r_i (vin_vs_r),
       .de_i (vin_de),
       .wd_i (gray),
       .rx_o (frm_x)

script/bitstream.tcl

@@ -1,3 +1,4 @@
 open_checkpoint post_route.dcp
 
 write_bitstream -force output.bit
+# write_debug_probes -force output.ltx