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M3 FW 0.1.6-beta3
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@jjwbruijn
jjwbruijn committed Sep 19, 2023
1 parent f924489 commit 0a43c60
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4 changes: 2 additions & 2 deletions ARM_Tag_FW/Newton_M3_nRF52811/core/packages/framework-arduinonordicnrf5/cores/nRF5/binary.h
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Original file line number Diff line number Diff line change
Expand Up @@ -20,15 +20,15 @@
#ifndef Binary_h
#define Binary_h

#define B0 0
//#define B0 0
#define B00 0
#define B000 0
#define B0000 0
#define B00000 0
#define B000000 0
#define B0000000 0
#define B00000000 0
#define B1 1
//#define B1 1
#define B01 1
#define B001 1
#define B0001 1
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286 changes: 143 additions & 143 deletions ...Tag_FW/Newton_M3_nRF52811/core/packages/framework-arduinonordicnrf5/libraries/SPI/SPI.cpp
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Expand Up @@ -33,89 +33,89 @@ const SPISettings DEFAULT_SPI_SETTINGS = SPISettings();

SPIClass::SPIClass(NRF_SPI_Type *p_spi, uint8_t uc_pinMISO, uint8_t uc_pinSCK, uint8_t uc_pinMOSI)
{
initialized = false;
assert(p_spi != NULL);
_p_spi = p_spi;
initialized = false;
assert(p_spi != NULL);
_p_spi = p_spi;

// pins
_uc_pinMiso = g_ADigitalPinMap[uc_pinMISO];
_uc_pinSCK = g_ADigitalPinMap[uc_pinSCK];
_uc_pinMosi = g_ADigitalPinMap[uc_pinMOSI];
// pins
_uc_pinMiso = g_ADigitalPinMap[uc_pinMISO];
_uc_pinSCK = g_ADigitalPinMap[uc_pinSCK];
_uc_pinMosi = g_ADigitalPinMap[uc_pinMOSI];

_dataMode = SPI_MODE0;
_bitOrder = SPI_CONFIG_ORDER_MsbFirst;
_dataMode = SPI_MODE0;
_bitOrder = SPI_CONFIG_ORDER_MsbFirst;
}

#ifdef ARDUINO_GENERIC
void SPIClass::setPins(uint8_t uc_pinMISO, uint8_t uc_pinSCK, uint8_t uc_pinMOSI)
{
_uc_pinMiso = g_ADigitalPinMap[uc_pinMISO];
_uc_pinSCK = g_ADigitalPinMap[uc_pinSCK];
_uc_pinMosi = g_ADigitalPinMap[uc_pinMOSI];
_uc_pinMiso = g_ADigitalPinMap[uc_pinMISO];
_uc_pinSCK = g_ADigitalPinMap[uc_pinSCK];
_uc_pinMosi = g_ADigitalPinMap[uc_pinMOSI];
}
#endif // ARDUINO_GENERIC

void SPIClass::begin()
{
init();
init();

_p_spi->PSELSCK = _uc_pinSCK;
_p_spi->PSELMOSI = _uc_pinMosi;
_p_spi->PSELMISO = _uc_pinMiso;
_p_spi->PSELSCK = _uc_pinSCK;
_p_spi->PSELMOSI = _uc_pinMosi;
_p_spi->PSELMISO = _uc_pinMiso;

config(DEFAULT_SPI_SETTINGS);
config(DEFAULT_SPI_SETTINGS);
}

void SPIClass::init()
{
if (initialized)
return;
interruptMode = SPI_IMODE_NONE;
interruptSave = 0;
interruptMask = 0;
initialized = true;
if (initialized)
return;
interruptMode = SPI_IMODE_NONE;
interruptSave = 0;
interruptMask = 0;
initialized = true;
}

void SPIClass::config(SPISettings settings)
{
_p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
_p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);

uint32_t config = settings.bitOrder;
uint32_t config = settings.bitOrder;

switch (settings.dataMode) {
default:
case SPI_MODE0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;
switch (settings.dataMode) {
default:
case SPI_MODE0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
case SPI_MODE1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;
case SPI_MODE2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}
case SPI_MODE3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}

_p_spi->CONFIG = config;
_p_spi->FREQUENCY = settings.clockFreq;
_p_spi->CONFIG = config;
_p_spi->FREQUENCY = settings.clockFreq;

_p_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
_p_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
}

void SPIClass::end()
{
_p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
_p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);

initialized = false;
initialized = false;
}

void SPIClass::usingInterrupt(int /*interruptNumber*/)
Expand All @@ -124,7 +124,7 @@ void SPIClass::usingInterrupt(int /*interruptNumber*/)

void SPIClass::beginTransaction(SPISettings settings)
{
config(settings);
config(settings);
}

void SPIClass::endTransaction(void)
Expand All @@ -133,133 +133,133 @@ void SPIClass::endTransaction(void)

void SPIClass::setBitOrder(BitOrder order)
{
this->_bitOrder = (order == MSBFIRST ? SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);

uint32_t config = this->_bitOrder;

switch (this->_dataMode) {
default:
case SPI_MODE0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}

_p_spi->CONFIG = config;
this->_bitOrder = (order == MSBFIRST ? SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);

uint32_t config = this->_bitOrder;

switch (this->_dataMode) {
default:
case SPI_MODE0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}

_p_spi->CONFIG = config;
}

void SPIClass::setDataMode(uint8_t mode)
{
this->_dataMode = mode;

uint32_t config = this->_bitOrder;

switch (this->_dataMode) {
default:
case SPI_MODE0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}

_p_spi->CONFIG = config;
this->_dataMode = mode;

uint32_t config = this->_bitOrder;

switch (this->_dataMode) {
default:
case SPI_MODE0:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE1:
config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE2:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
break;

case SPI_MODE3:
config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
break;
}

_p_spi->CONFIG = config;
}

void SPIClass::setClockDivider(uint8_t div)
{
uint32_t clockFreq;

if (div >= SPI_CLOCK_DIV128) {
clockFreq = SPI_FREQUENCY_FREQUENCY_K125;
} else if (div >= SPI_CLOCK_DIV64) {
clockFreq = SPI_FREQUENCY_FREQUENCY_K250;
} else if (div >= SPI_CLOCK_DIV32) {
clockFreq = SPI_FREQUENCY_FREQUENCY_K500;
} else if (div >= SPI_CLOCK_DIV16) {
clockFreq = SPI_FREQUENCY_FREQUENCY_M1;
} else if (div >= SPI_CLOCK_DIV8) {
clockFreq = SPI_FREQUENCY_FREQUENCY_M2;
} else if (div >= SPI_CLOCK_DIV4) {
clockFreq = SPI_FREQUENCY_FREQUENCY_M4;
} else {
clockFreq = SPI_FREQUENCY_FREQUENCY_M8;
}

_p_spi->FREQUENCY = clockFreq;
uint32_t clockFreq;

if (div >= SPI_CLOCK_DIV128) {
clockFreq = SPI_FREQUENCY_FREQUENCY_K125;
} else if (div >= SPI_CLOCK_DIV64) {
clockFreq = SPI_FREQUENCY_FREQUENCY_K250;
} else if (div >= SPI_CLOCK_DIV32) {
clockFreq = SPI_FREQUENCY_FREQUENCY_K500;
} else if (div >= SPI_CLOCK_DIV16) {
clockFreq = SPI_FREQUENCY_FREQUENCY_M1;
} else if (div >= SPI_CLOCK_DIV8) {
clockFreq = SPI_FREQUENCY_FREQUENCY_M2;
} else if (div >= SPI_CLOCK_DIV4) {
clockFreq = SPI_FREQUENCY_FREQUENCY_M4;
} else {
clockFreq = SPI_FREQUENCY_FREQUENCY_M8;
}

_p_spi->FREQUENCY = clockFreq;
}

byte SPIClass::transfer(uint8_t data)
{
_p_spi->TXD = data;
_p_spi->TXD = data;

while(!_p_spi->EVENTS_READY);
while(!_p_spi->EVENTS_READY);

data = _p_spi->RXD;
data = _p_spi->RXD;

_p_spi->EVENTS_READY = 0x0UL;
_p_spi->EVENTS_READY = 0x0UL;

return data;
return data;
}

uint16_t SPIClass::transfer16(uint16_t data) {
union { uint16_t val; struct { uint8_t lsb; uint8_t msb; }; } t;
union { uint16_t val; struct { uint8_t lsb; uint8_t msb; }; } t;

t.val = data;
t.val = data;

if (_bitOrder == SPI_CONFIG_ORDER_LsbFirst) {
t.lsb = transfer(t.lsb);
t.msb = transfer(t.msb);
} else {
t.msb = transfer(t.msb);
t.lsb = transfer(t.lsb);
}
if (_bitOrder == SPI_CONFIG_ORDER_LsbFirst) {
t.lsb = transfer(t.lsb);
t.msb = transfer(t.msb);
} else {
t.msb = transfer(t.msb);
t.lsb = transfer(t.lsb);
}

return t.val;
return t.val;
}

void SPIClass::attachInterrupt() {
// Should be enableInterrupt()
// Should be enableInterrupt()
}

void SPIClass::detachInterrupt() {
// Should be disableInterrupt()
// Should be disableInterrupt()
}

#if SPI_INTERFACES_COUNT > 0
#if defined(NRF52_SERIES) && !defined(NRF52811_XXAA)
SPIClass SPI (NRF_SPI2, PIN_SPI_MISO, PIN_SPI_SCK, PIN_SPI_MOSI);
#else
SPIClass SPI (NRF_SPI0, PIN_SPI_MISO, PIN_SPI_SCK, PIN_SPI_MOSI);
// SPIClass SPI (NRF_SPI0, PIN_SPI_MISO, PIN_SPI_SCK, PIN_SPI_MOSI);
#endif
#endif

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