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Hardcoded address width in bsg_cache_to_dram_ctrl #532

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dpetrisko opened this issue Dec 9, 2021 · 1 comment
Open

Hardcoded address width in bsg_cache_to_dram_ctrl #532

dpetrisko opened this issue Dec 9, 2021 · 1 comment
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dpetrisko commented Dec 9, 2021 •
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basejump_stl/bsg_cache/bsg_cache_to_dram_ctrl.v

Line 214 in c704701

4: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[29-$clog2(num_cache_p)-1:0]});

num_cache_p > 1 does not necessarily mean shorter address per cache, only if addresses are hashed by top bits
@dpetrisko dpetrisko added the bug Something isn't working label Dec 9, 2021
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dpetrisko commented Dec 9, 2021 •
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Additionally, the code will not compile for addr_width < 29 and num_cache_p == 1

dpetrisko pushed a commit that referenced this issue Jan 26, 2023
@tommydcjung
Memtest fast (#532)
7d3aeeb 
* memtest_fast

* memtest_fast

* no volatile

* shorten
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