flwadd

v/vanilla_bean/alu.v

@@ -53,7 +53,7 @@ always_comb
       `RV32_AUIPC:
         result_o = `RV32_signext_Uimm(op_i) + pc_plus4_i - 3'b100;
 
-      `RV32_ADDI, `RV32_ADD:
+      `RV32_ADDI, `RV32_ADD, `RV32_FLWADD:
         begin
           result_o = sum[31:0];
           sub_not_add = 1'b0;

v/vanilla_bean/bsg_vanilla_pkg.v

@@ -112,6 +112,7 @@ typedef struct packed {
   logic is_byte_op;       // Op is byte load/store
   logic is_hex_op;        // Op is hex load/store
   logic is_load_unsigned; // Op is unsigned load
+  logic is_flwadd_op;     // flwadd
 
   // Branch & Jump
   logic is_branch_op;
@@ -539,4 +540,23 @@ typedef struct packed {
 `define RV32_FSQRT_S  {7'b0101100, 5'b00000, 5'b?????, 3'b???, 5'b?????, 7'b1010011}
 
 
+
+// NON-STANDARD RISC-V Instructions
+
+//  [FLWADD]
+//
+//  Assembly format
+//  flwadd fd, rs2, 0(rs1)
+//
+//  Semantic:
+//  fd = *rs1; rs1 = rs1 + rs2;
+//
+//  Machine Format:
+//          rs1   rs2       rd    opcode
+//  0000000_?????_?????_111_?????_0000111
+`define RV32_FLWADD_OP     7'b0000100
+`define RV32_FLWADD {7'b0000000, 5'b?????, 5'b?????, 3'b111, 5'b?????, `RV32_FLWADD_OP}
+
+
+
 endpackage

v/vanilla_bean/cl_decode.v

@@ -32,7 +32,7 @@ always_comb begin
       `RV32_LUI_OP, `RV32_AUIPC_OP,
       `RV32_JAL_OP, `RV32_JALR_OP,
       `RV32_LOAD, `RV32_OP,
-      `RV32_OP_IMM, `RV32_AMO_OP: begin
+      `RV32_OP_IMM, `RV32_AMO_OP, `RV32_FLWADD_OP: begin
         decode_o.write_rd = 1'b1;
       end
       `RV32_OP_FP: begin
@@ -57,7 +57,7 @@ always_comb begin
     `RV32_JALR_OP, `RV32_BRANCH,
     `RV32_LOAD, `RV32_STORE,
     `RV32_OP, `RV32_OP_IMM,
-    `RV32_AMO_OP: begin
+    `RV32_AMO_OP, `RV32_FLWADD_OP: begin
       decode_o.read_rs1 = 1'b1;
     end
    `RV32_OP_FP: begin
@@ -87,7 +87,7 @@ end
 // declares if Op reads from second port of register file
 always_comb begin
   unique casez (instruction_i.op)
-    `RV32_BRANCH, `RV32_STORE, `RV32_OP: begin
+    `RV32_BRANCH, `RV32_STORE, `RV32_OP, `RV32_FLWADD_OP: begin
       decode_o.read_rs2 = 1'b1;
     end
     `RV32_AMO_OP: begin
@@ -103,6 +103,7 @@ always_comb begin
 end
 
 // Load & Store
+assign decode_o.is_flwadd_op = (instruction_i.op == `RV32_FLWADD_OP);
 assign decode_o.is_load_op = (instruction_i.op == `RV32_LOAD) | (instruction_i.op == `RV32_LOAD_FP);
 assign decode_o.is_store_op = (instruction_i.op == `RV32_STORE) | (instruction_i.op == `RV32_STORE_FP);
 
@@ -322,6 +323,14 @@ always_comb begin
       decode_o.write_frd = 1'b1;
       decode_o.is_fp_op = 1'b1;
     end
+    // FLWADD
+    `RV32_FLWADD: begin
+      decode_o.read_frs1 = 1'b0;
+      decode_o.read_frs2 = 1'b0;
+      decode_o.read_frs3 = 1'b0;
+      decode_o.write_frd = 1'b1;
+      decode_o.is_fp_op = 1'b0;
+    end
     default: begin
       decode_o.read_frs1 = 1'b0;
       decode_o.read_frs2 = 1'b0;

v/vanilla_bean/lsu.v

@@ -97,7 +97,7 @@ module lsu
 
   assign dmem_v_o = is_local_dmem_addr &
     (exe_decode_i.is_load_op | exe_decode_i.is_store_op |
-     exe_decode_i.is_lr_op | exe_decode_i.is_lr_aq_op);
+     exe_decode_i.is_lr_op | exe_decode_i.is_lr_aq_op | exe_decode_i.is_flwadd_op);
   assign dmem_w_o = exe_decode_i.is_store_op;
   assign dmem_addr_o = mem_addr[2+:dmem_addr_width_lp]; 
   assign dmem_data_o = store_data;
@@ -152,7 +152,7 @@ module lsu
 
 
   assign remote_req_v_o = icache_miss_i |
-    ((exe_decode_i.is_load_op | exe_decode_i.is_store_op | exe_decode_i.is_amo_op) & ~is_local_dmem_addr);
+    ((exe_decode_i.is_load_op | exe_decode_i.is_store_op | exe_decode_i.is_amo_op | exe_decode_i.is_flwadd_op) & ~is_local_dmem_addr);
 
   // reserve
   // only valid on local DMEM

v/vanilla_bean/vanilla_core.v

@@ -396,7 +396,7 @@ module vanilla_core
     | id_r.decode.is_lr_aq_op
     | id_r.decode.is_amo_op;
 
-  wire [data_width_p-1:0] mem_addr_op2 = is_amo_or_lr_op
+  wire [data_width_p-1:0] mem_addr_op2 = (is_amo_or_lr_op | id_r.decode.is_flwadd_op)
     ? '0
     : (id_r.decode.is_store_op
       ? `RV32_signext_Simm(id_r.instruction)
@@ -1213,7 +1213,7 @@ module vanilla_core
   wire id_rs2_non_zero = id_rs2 != '0;
   wire id_rd_non_zero = id_rd != '0;
   wire int_remote_load_in_exe = remote_req_in_exe & exe_r.decode.is_load_op & exe_r.decode.write_rd;
-  wire float_remote_load_in_exe = remote_req_in_exe & exe_r.decode.is_load_op & exe_r.decode.write_frd;
+  wire float_remote_load_in_exe = remote_req_in_exe & (exe_r.decode.is_load_op | exe_r.decode.is_flwadd_op) & exe_r.decode.write_frd;
   wire fdiv_fsqrt_in_fp_exe = fp_exe_r.fp_decode.is_fdiv_op | fp_exe_r.fp_decode.is_fsqrt_op;
   wire remote_credit_pending = (out_credits_i != max_out_credits_p);
 
@@ -1286,7 +1286,8 @@ module vanilla_core
     |id_r.decode.is_store_op
     |id_r.decode.is_amo_op
     |id_r.decode.is_lr_aq_op
-    |id_r.decode.is_lr_op);
+    |id_r.decode.is_lr_op
+    |id_r.decode.is_flwadd_op);
 
   // stall_amo_rl
   // If there is a remote request in EXE, there is a technically remote request pending, even if the credit counter has not yet been decremented.
@@ -1297,7 +1298,7 @@ module vanilla_core
   // stall_remote_req
   logic [lg_fwd_fifo_els_lp-1:0] remote_req_counter_r;
   wire local_mem_op_restore = (lsu_dmem_v_lo & ~exe_r.decode.is_lr_op & ~exe_r.decode.is_lr_aq_op) & ~stall_all;
-  wire id_remote_req_op = (id_r.decode.is_load_op | id_r.decode.is_store_op | id_r.decode.is_amo_op | id_r.icache_miss);
+  wire id_remote_req_op = (id_r.decode.is_load_op | id_r.decode.is_store_op | id_r.decode.is_amo_op | id_r.icache_miss | id_r.decode.is_flwadd_op);
   wire memory_op_issued = id_remote_req_op & ~flush & ~stall_id & ~stall_all;
   wire [lg_fwd_fifo_els_lp-1:0] remote_req_available =
     remote_req_counter_r +