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Add i8,u8 support (#575)
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* Add i8 and u8 vector types
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AlessandroCanossa authored Oct 30, 2024
1 parent e2f4be9 commit 6f9af89
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4 changes: 4 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,10 @@ and feel of the API has solidified.
* square matrices: `DMat2`, `DMat3` and `DMat4`
* a quaternion type: `DQuat`
* affine transformation types: `DAffine2` and `DAffine3`
* `i8` types
* vectors: `I8Vec2`, `I8Vec3` and `I8Vec4`
* `u8` types
* vectors: `U16Vec2`, `U16Vec3` and `U16Vec4`
* `i16` types
* vectors: `I16Vec2`, `I16Vec3` and `I16Vec4`
* `u16` types
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78 changes: 78 additions & 0 deletions codegen/src/outputs.rs
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,30 @@ impl ContextBuilder {
Self::new_tvecn_swizzle_impl(4, "D")
}

pub fn new_i8vec2_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(2, "I8")
}

pub fn new_i8vec3_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(3, "I8")
}

pub fn new_i8vec4_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(4, "I8")
}

pub fn new_u8vec2_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(2, "U8")
}

pub fn new_u8vec3_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(3, "U8")
}

pub fn new_u8vec4_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(4, "U8")
}

pub fn new_i16vec2_swizzle_impl() -> Self {
Self::new_tvecn_swizzle_impl(2, "I16")
}
Expand Down Expand Up @@ -225,6 +249,30 @@ impl ContextBuilder {
Self::new_vecn(4).with_scalar_t("f64")
}

pub fn new_i8vec2() -> Self {
Self::new_vecn(2).with_scalar_t("i8")
}

pub fn new_i8vec3() -> Self {
Self::new_vecn(3).with_scalar_t("i8")
}

pub fn new_i8vec4() -> Self {
Self::new_vecn(4).with_scalar_t("i8")
}

pub fn new_u8vec2() -> Self {
Self::new_vecn(2).with_scalar_t("u8")
}

pub fn new_u8vec3() -> Self {
Self::new_vecn(3).with_scalar_t("u8")
}

pub fn new_u8vec4() -> Self {
Self::new_vecn(4).with_scalar_t("u8")
}

pub fn new_i16vec2() -> Self {
Self::new_vecn(2).with_scalar_t("i16")
}
Expand Down Expand Up @@ -488,6 +536,30 @@ pub fn build_output_pairs() -> HashMap<&'static str, tera::Context> {
"src/swizzles/dvec4_impl.rs",
ContextBuilder::new_dvec4_swizzle_impl().build(),
),
(
"src/swizzles/i8vec2_impl.rs",
ContextBuilder::new_i8vec2_swizzle_impl().build(),
),
(
"src/swizzles/i8vec3_impl.rs",
ContextBuilder::new_i8vec3_swizzle_impl().build(),
),
(
"src/swizzles/i8vec4_impl.rs",
ContextBuilder::new_i8vec4_swizzle_impl().build(),
),
(
"src/swizzles/u8vec2_impl.rs",
ContextBuilder::new_u8vec2_swizzle_impl().build(),
),
(
"src/swizzles/u8vec3_impl.rs",
ContextBuilder::new_u8vec3_swizzle_impl().build(),
),
(
"src/swizzles/u8vec4_impl.rs",
ContextBuilder::new_u8vec4_swizzle_impl().build(),
),
(
"src/swizzles/i16vec2_impl.rs",
ContextBuilder::new_i16vec2_swizzle_impl().build(),
Expand Down Expand Up @@ -658,6 +730,12 @@ pub fn build_output_pairs() -> HashMap<&'static str, tera::Context> {
("src/f64/dvec2.rs", ContextBuilder::new_dvec2().build()),
("src/f64/dvec3.rs", ContextBuilder::new_dvec3().build()),
("src/f64/dvec4.rs", ContextBuilder::new_dvec4().build()),
("src/i8/i8vec2.rs", ContextBuilder::new_i8vec2().build()),
("src/i8/i8vec3.rs", ContextBuilder::new_i8vec3().build()),
("src/i8/i8vec4.rs", ContextBuilder::new_i8vec4().build()),
("src/u8/u8vec2.rs", ContextBuilder::new_u8vec2().build()),
("src/u8/u8vec3.rs", ContextBuilder::new_u8vec3().build()),
("src/u8/u8vec4.rs", ContextBuilder::new_u8vec4().build()),
("src/i16/i16vec2.rs", ContextBuilder::new_i16vec2().build()),
("src/i16/i16vec3.rs", ContextBuilder::new_i16vec3().build()),
("src/i16/i16vec4.rs", ContextBuilder::new_i16vec4().build()),
Expand Down
90 changes: 81 additions & 9 deletions codegen/templates/vec.rs.tera
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,24 @@
{% set vec4_t = "DVec4" %}
{% set from_types = ["Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim] %}
{% endif %}
{% elif scalar_t == "i8" %}
{% set is_signed = true %}
{% set is_float = false %}
{% set self_t = "I8Vec" ~ dim %}
{% set opposite_signedness_t = "U8Vec" ~ dim %}
{% set vec2_t = "I8Vec2" %}
{% set vec3_t = "I8Vec3" %}
{% set vec4_t = "I8Vec4" %}
{% set try_from_types = ["U8Vec" ~ dim, "I16Vec" ~ dim, "U16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% elif scalar_t == "u8" %}
{% set is_signed = false %}
{% set is_float = false %}
{% set self_t = "U8Vec" ~ dim %}
{% set opposite_signedness_t = "I8Vec" ~ dim %}
{% set vec2_t = "U8Vec2" %}
{% set vec3_t = "U8Vec3" %}
{% set vec4_t = "U8Vec4" %}
{% set try_from_types = ["I8Vec" ~ dim, "I16Vec" ~ dim, "U16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% elif scalar_t == "i16" %}
{% set is_signed = true %}
{% set is_float = false %}
Expand All @@ -49,6 +67,7 @@
{% set vec2_t = "I16Vec2" %}
{% set vec3_t = "I16Vec3" %}
{% set vec4_t = "I16Vec4" %}
{% set from_types = ["I8Vec" ~ dim, "U8Vec" ~ dim] %}
{% set try_from_types = ["U16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% elif scalar_t == "u16" %}
{% set is_signed = false %}
Expand All @@ -58,7 +77,8 @@
{% set vec2_t = "U16Vec2" %}
{% set vec3_t = "U16Vec3" %}
{% set vec4_t = "U16Vec4" %}
{% set try_from_types = ["I16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% set from_types = ["U8Vec" ~ dim] %}
{% set try_from_types = ["I8Vec" ~ dim, "I16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% elif scalar_t == "i32" %}
{% set is_signed = true %}
{% set is_float = false %}
Expand All @@ -67,7 +87,7 @@
{% set vec2_t = "IVec2" %}
{% set vec3_t = "IVec3" %}
{% set vec4_t = "IVec4" %}
{% set from_types = ["I16Vec" ~ dim, "U16Vec" ~ dim] %}
{% set from_types = ["I8Vec" ~ dim, "U8Vec" ~ dim, "I16Vec" ~ dim, "U16Vec" ~ dim] %}
{% set try_from_types = ["UVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% elif scalar_t == "u32" %}
{% set is_signed = false %}
Expand All @@ -77,8 +97,8 @@
{% set vec2_t = "UVec2" %}
{% set vec3_t = "UVec3" %}
{% set vec4_t = "UVec4" %}
{% set from_types = ["U16Vec" ~ dim] %}
{% set try_from_types = ["I16Vec" ~ dim, "IVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% set from_types = ["U8Vec" ~ dim, "U16Vec" ~ dim] %}
{% set try_from_types = ["I8Vec" ~ dim, "I16Vec" ~ dim, "IVec" ~ dim, "I64Vec" ~ dim, "U64Vec" ~ dim] %}
{% elif scalar_t == "i64" %}
{% set is_signed = true %}
{% set is_float = false %}
Expand All @@ -87,7 +107,7 @@
{% set vec2_t = "I64Vec2" %}
{% set vec3_t = "I64Vec3" %}
{% set vec4_t = "I64Vec4" %}
{% set from_types = ["I16Vec" ~ dim, "U16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim] %}
{% set from_types = ["I8Vec" ~ dim, "U8Vec" ~ dim, "I16Vec" ~ dim, "U16Vec" ~ dim, "IVec" ~ dim, "UVec" ~ dim] %}
{% set try_from_types = ["U64Vec" ~ dim] %}
{% elif scalar_t == "u64" %}
{% set is_signed = false %}
Expand All @@ -97,24 +117,28 @@
{% set vec2_t = "U64Vec2" %}
{% set vec3_t = "U64Vec3" %}
{% set vec4_t = "U64Vec4" %}
{% set from_types = ["U16Vec" ~ dim, "UVec" ~ dim] %}
{% set try_from_types = ["I16Vec" ~ dim, "IVec" ~ dim, "I64Vec" ~ dim] %}
{% set from_types = ["U8Vec" ~ dim, "U16Vec" ~ dim, "UVec" ~ dim] %}
{% set try_from_types = ["I8Vec" ~ dim, "I16Vec" ~ dim, "IVec" ~ dim, "I64Vec" ~ dim] %}
{% endif %}
{% set bvec_from_type = "BVec" ~ dim %}
{% if dim > 2 %}
{% set bveca_from_type = "BVec" ~ dim ~ "A" %}
{% endif %}

{% if dim == 2 %}
{% if scalar_t == "i16" or scalar_t == "u16" %}
{% if scalar_t == "i8" or scalar_t == "u8" %}
{% set cuda_align = 2 %}
{% elif scalar_t == "i16" or scalar_t == "u16" %}
{% set cuda_align = 4 %}
{% elif scalar_t == "f32" or scalar_t == "i32" or scalar_t == "u32" %}
{% set cuda_align = 8 %}
{% elif scalar_t == "f64" or scalar_t == "i64" or scalar_t == "u64" %}
{% set cuda_align = 16 %}
{% endif %}
{% elif dim == 4 %}
{% if scalar_t == "i16" or scalar_t == "u16" %}
{% if scalar_t == "i8" or scalar_t == "u8" %}
{% set cuda_align = 4 %}
{% elif scalar_t == "i16" or scalar_t == "u16" %}
{% set cuda_align = 8 %}
{% elif scalar_t == "f32" or scalar_t == "i32" or scalar_t == "u32" %}
{% set cuda_align = 16 %}
Expand Down Expand Up @@ -2252,6 +2276,54 @@ impl {{ self_t }} {
}
{% endif %}
{% endif %}
{% if scalar_t != "i8" %}
{% if dim == 2 %}
/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec2(&self) -> crate::I8Vec2 {
crate::I8Vec2::new(self.x as i8, self.y as i8)
}
{% elif dim == 3 %}
/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec3(&self) -> crate::I8Vec3 {
crate::I8Vec3::new(self.x as i8, self.y as i8, self.z as i8)
}
{% elif dim == 4 %}
/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec4(&self) -> crate::I8Vec4 {
crate::I8Vec4::new(self.x as i8, self.y as i8, self.z as i8, self.w as i8)
}
{% endif %}
{% endif %}
{% if scalar_t != "u8" %}
{% if dim == 2 %}
/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec2(&self) -> crate::U8Vec2 {
crate::U8Vec2::new(self.x as u8, self.y as u8)
}
{% elif dim == 3 %}
/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec3(&self) -> crate::U8Vec3 {
crate::U8Vec3::new(self.x as u8, self.y as u8, self.z as u8)
}
{% elif dim == 4 %}
/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec4(&self) -> crate::U8Vec4 {
crate::U8Vec4::new(self.x as u8, self.y as u8, self.z as u8, self.w as u8)
}
{% endif %}
{% endif %}
{% if scalar_t != "i16" %}
{% if dim == 2 %}
/// Casts all elements of `self` to `i16`.
Expand Down
14 changes: 14 additions & 0 deletions src/f32/coresimd/vec3a.rs
Original file line number Diff line number Diff line change
Expand Up @@ -946,6 +946,20 @@ impl Vec3A {
crate::DVec3::new(self.x as f64, self.y as f64, self.z as f64)
}

/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec3(&self) -> crate::I8Vec3 {
crate::I8Vec3::new(self.x as i8, self.y as i8, self.z as i8)
}

/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec3(&self) -> crate::U8Vec3 {
crate::U8Vec3::new(self.x as u8, self.y as u8, self.z as u8)
}

/// Casts all elements of `self` to `i16`.
#[inline]
#[must_use]
Expand Down
14 changes: 14 additions & 0 deletions src/f32/coresimd/vec4.rs
Original file line number Diff line number Diff line change
Expand Up @@ -865,6 +865,20 @@ impl Vec4 {
crate::DVec4::new(self.x as f64, self.y as f64, self.z as f64, self.w as f64)
}

/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec4(&self) -> crate::I8Vec4 {
crate::I8Vec4::new(self.x as i8, self.y as i8, self.z as i8, self.w as i8)
}

/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec4(&self) -> crate::U8Vec4 {
crate::U8Vec4::new(self.x as u8, self.y as u8, self.z as u8, self.w as u8)
}

/// Casts all elements of `self` to `i16`.
#[inline]
#[must_use]
Expand Down
14 changes: 14 additions & 0 deletions src/f32/neon/vec3a.rs
Original file line number Diff line number Diff line change
Expand Up @@ -990,6 +990,20 @@ impl Vec3A {
crate::DVec3::new(self.x as f64, self.y as f64, self.z as f64)
}

/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec3(&self) -> crate::I8Vec3 {
crate::I8Vec3::new(self.x as i8, self.y as i8, self.z as i8)
}

/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec3(&self) -> crate::U8Vec3 {
crate::U8Vec3::new(self.x as u8, self.y as u8, self.z as u8)
}

/// Casts all elements of `self` to `i16`.
#[inline]
#[must_use]
Expand Down
14 changes: 14 additions & 0 deletions src/f32/neon/vec4.rs
Original file line number Diff line number Diff line change
Expand Up @@ -902,6 +902,20 @@ impl Vec4 {
crate::DVec4::new(self.x as f64, self.y as f64, self.z as f64, self.w as f64)
}

/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec4(&self) -> crate::I8Vec4 {
crate::I8Vec4::new(self.x as i8, self.y as i8, self.z as i8, self.w as i8)
}

/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec4(&self) -> crate::U8Vec4 {
crate::U8Vec4::new(self.x as u8, self.y as u8, self.z as u8, self.w as u8)
}

/// Casts all elements of `self` to `i16`.
#[inline]
#[must_use]
Expand Down
14 changes: 14 additions & 0 deletions src/f32/scalar/vec3a.rs
Original file line number Diff line number Diff line change
Expand Up @@ -993,6 +993,20 @@ impl Vec3A {
crate::DVec3::new(self.x as f64, self.y as f64, self.z as f64)
}

/// Casts all elements of `self` to `i8`.
#[inline]
#[must_use]
pub fn as_i8vec3(&self) -> crate::I8Vec3 {
crate::I8Vec3::new(self.x as i8, self.y as i8, self.z as i8)
}

/// Casts all elements of `self` to `u8`.
#[inline]
#[must_use]
pub fn as_u8vec3(&self) -> crate::U8Vec3 {
crate::U8Vec3::new(self.x as u8, self.y as u8, self.z as u8)
}

/// Casts all elements of `self` to `i16`.
#[inline]
#[must_use]
Expand Down
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