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Updated PT, modified V and added VT. #1

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Updated PT, modified V and added VT. #1

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0d85d04
Adding blackparrot termination conditions
dpetrisko Apr 24, 2019
24cf46c
changed V env to use M mode instead of S
farzamgl Apr 24, 2019
1c0b36c
added fake ufinish CSR for simulation end
farzamgl Apr 25, 2019
1423706
Adding link to our mtvec handler
dpetrisko Apr 25, 2019
0a3d6bc
Simplifying termination condition
dpetrisko Apr 25, 2019
1a8e080
functions incorporated
Apr 26, 2019
14428d0
start point
Apr 28, 2019
79cb643
timer environment add
Apr 29, 2019
2109241
macro applyed
Apr 29, 2019
27542f1
revert v
Apr 29, 2019
e6a8f25
macro name changed unncessary constant removed
Apr 29, 2019
37fde77
backup file removed
Apr 29, 2019
46293c3
v in bp_mode recovered
Apr 29, 2019
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10 changes: 9 additions & 1 deletion encoding.h
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
#define MSTATUS_UXL 0x0000000300000000
#define MSTATUS_SXL 0x0000000C00000000
#define MSTATUS64_SD 0x8000000000000000
#define MSTATUS_MPP_OFFSET 11

#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
Expand Down Expand Up @@ -166,11 +167,18 @@
#define PTE_A 0x040 // Accessed
#define PTE_D 0x080 // Dirty
#define PTE_SOFT 0x300 // Reserved for Software

#define PTE_PPN_SHIFT 10
#define PTE_PPN_OFFSET 2
#define MASK_PTE_PPN 0x3ffffffffffc00
#define PTE_OFF 3

#define PPN 0xfffffffffff

#define PGOFF 12

#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)


#ifdef __riscv

#if __riscv_xlen == 64
Expand Down
32 changes: 23 additions & 9 deletions p/riscv_test.h
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Original file line number Diff line number Diff line change
Expand Up @@ -111,6 +111,7 @@
.align 6; \
.weak stvec_handler; \
.weak mtvec_handler; \
.weak bp_mtvec_handler; \
.globl _start; \
_start: \
/* reset vector */ \
Expand All @@ -135,6 +136,11 @@ trap_vector: \
INTERRUPT_HANDLER; \
handle_exception: \
/* we don't know how to handle whatever the exception was */ \
/* ... but blackparrot does! */ \
li sp, 0x0000_0000_8FFF_DFFF; \
la t5, bp_mtvec_handler; \
beqz t5, other_exception; \
jr t5; \
other_exception: \
/* some unhandlable exception occurred */ \
1: ori TESTNUM, TESTNUM, 1337; \
Expand Down Expand Up @@ -183,19 +189,27 @@ reset_vector: \
//-----------------------------------------------------------------------
// Pass/Fail Macro
//-----------------------------------------------------------------------

// BP: Modified to work with BlackParrot termination condition
#define RVTEST_PASS \
fence; \
li TESTNUM, 1; \
ecall

li a0, 0; \
csrw 0x800, a0; \
// \
//fence; \
//li TESTNUM, 1; \
//ecall

// BP: Modified to work with BlackParrot termination condition
#define TESTNUM gp
#define RVTEST_FAIL \
fence; \
1: beqz TESTNUM, 1b; \
sll TESTNUM, TESTNUM, 1; \
or TESTNUM, TESTNUM, 1; \
ecall
li a0, -1; \
csrw 0x800, a0; \
// \
//fence; \
1: //beqz TESTNUM, 1b; \
//sll TESTNUM, TESTNUM, 1; \
//or TESTNUM, TESTNUM, 1; \
//ecall

//-----------------------------------------------------------------------
// Data Section Macro
Expand Down
28 changes: 22 additions & 6 deletions pt/riscv_test.h
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Expand Up @@ -5,15 +5,26 @@

#include "../p/riscv_test.h"

#define TIMER_INTERVAL 2
#define TIMER_INTERVAL 50
#define MTIME_BASE 0x0200BFF8
#define MTIMECMP_BASE 0x02004000
#define MTIMECMP_SHIFT 3 // 64 bits for rv32/64

#undef EXTRA_INIT_TIMER
#define EXTRA_INIT_TIMER \
li a0, MIP_MTIP; \
csrs mie, a0; \
csrr a0, mtime; \
addi a0, a0, TIMER_INTERVAL; \
csrw mtimecmp, a0; \
csrr t0, mstatus; \
ori t0, t0, MSTATUS_MPIE; \
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Why are you changing PIE here?

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on mret. mie in mstatus will become mpie in mstatus. mie in mstatus is the global interrupt enable signal.

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That’s done in hardware

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Yes. If I do not write MPIE before mret, MIE will be clearer after mret.

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No it won’t. On the timer interrupt, MPIE becomes MIE (1) in hardware. On MRET, MIE becomes MPIE (1)

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Because on MRET, MIE becomes MPIE. I write MPIE to 1 to before MRET to enable timer interrupt after MRE.

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You’re not understanding. MPIE is already 1 when you’re in the trap. If it weren’t, you wouldn’t have taken the trap

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Look at how the old spike code worked. They didn’t need to write to MPIE

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This MPIE is only for initialization. During reset mstatus was all zeros.

csrw mstatus, t0; \
li t0, MTIME_BASE; /* mtime address */ \
li t1, MTIMECMP_BASE; \
csrr t2, mhartid; \
slli t2, t2, MTIMECMP_SHIFT; \
add t1, t1, t2; /* mtimecmp address */ \
ld a0, 0(t0); /* csrr a0, mtime */ \
addi a0, a0, TIMER_INTERVAL; \
sd a0, 0(t1); /* csrw mtimecmp, a0 */ \

#if SSTATUS_XS != 0x18000
# error
Expand All @@ -26,9 +37,14 @@
srli t5, t5, 1; \
add t5, t5, -IRQ_M_TIMER; \
bnez t5, other_exception; /* other interrups shouldn't happen */\
csrr t5, mtime; \
li t0, MTIME_BASE; /* mtime address */ \
li t1, MTIMECMP_BASE; \
csrr t2, mhartid; \
slli t2, t2, MTIMECMP_SHIFT; \
add t1, t1, t2; /* mtimecmp address */ \
ld t5, 0(t0); /* csrr t5, mtime */ \
addi t5, t5, TIMER_INTERVAL; \
csrw mtimecmp, t5; \
sd t5, 0(t1); /* csrw mtimecmp, t5 */ \
mret; \

//-----------------------------------------------------------------------
Expand Down
18 changes: 9 additions & 9 deletions v/entry.S
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Expand Up @@ -25,7 +25,7 @@ nmi_vector:

.align 2
trap_vector:
j wtf
j trap_entry

handle_reset:
la t0, trap_vector
Expand All @@ -42,7 +42,7 @@ handle_reset:
.globl pop_tf
pop_tf:
LOAD t0,33*REGBYTES(a0)
csrw sepc,t0
csrw mepc,t0
LOAD x1,1*REGBYTES(a0)
LOAD x2,2*REGBYTES(a0)
LOAD x3,3*REGBYTES(a0)
Expand Down Expand Up @@ -74,12 +74,12 @@ pop_tf:
LOAD x30,30*REGBYTES(a0)
LOAD x31,31*REGBYTES(a0)
LOAD a0,10*REGBYTES(a0)
sret
mret

.global trap_entry
.align 2
trap_entry:
csrrw sp, sscratch, sp
csrrw sp, mscratch, sp

# save gprs
STORE x1,1*REGBYTES(sp)
Expand Down Expand Up @@ -113,17 +113,17 @@ trap_entry:
STORE x30,30*REGBYTES(sp)
STORE x31,31*REGBYTES(sp)

csrrw t0,sscratch,sp
csrrw t0,mscratch,sp
STORE t0,2*REGBYTES(sp)

# get sr, epc, badvaddr, cause
csrr t0,sstatus
csrr t0,mstatus
STORE t0,32*REGBYTES(sp)
csrr t0,sepc
csrr t0,mepc
STORE t0,33*REGBYTES(sp)
csrr t0,sbadaddr
csrr t0,mbadaddr
STORE t0,34*REGBYTES(sp)
csrr t0,scause
csrr t0,mcause
STORE t0,35*REGBYTES(sp)

move a0, sp
Expand Down
8 changes: 4 additions & 4 deletions v/riscv_test.h
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Expand Up @@ -27,11 +27,11 @@ userstart: \
// Pass/Fail Macro
//-----------------------------------------------------------------------

#undef RVTEST_PASS
#define RVTEST_PASS li a0, 1; scall
//#undef RVTEST_PASS
//#define RVTEST_PASS li a0, 1; scall

#undef RVTEST_FAIL
#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;
//#undef RVTEST_FAIL
//#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;

//-----------------------------------------------------------------------
// Data Section Macro
Expand Down
38 changes: 19 additions & 19 deletions v/vm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,7 @@ void handle_fault(uintptr_t addr, uintptr_t cause)
assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
user_llpt[addr/PGSIZE] |= PTE_D;
}
flush_page(addr);
//flush_page(addr);
return;
}

Expand All @@ -160,17 +160,17 @@ void handle_fault(uintptr_t addr, uintptr_t cause)

uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
flush_page(addr);
//flush_page(addr);

assert(user_mapping[addr/PGSIZE].addr == 0);
user_mapping[addr/PGSIZE] = *node;

uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
memcpy((void*)addr, uva2kva(addr), PGSIZE);
write_csr(sstatus, sstatus);
//uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
memcpy((void*)(node->addr), (void*)(DRAM_BASE + addr), PGSIZE);
//write_csr(sstatus, sstatus);

user_llpt[addr/PGSIZE] = new_pte;
flush_page(addr);
//user_llpt[addr/PGSIZE] = new_pte;
//flush_page(addr);

__builtin___clear_cache(0,0);
}
Expand Down Expand Up @@ -263,32 +263,32 @@ void vm_boot(uintptr_t test_addr)
uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1;
asm volatile ("la t0, 1f\n\t"
"csrrw t0, mtvec, t0\n\t"
// "csrrw t0, mtvec, t0\n\t"
"csrw pmpaddr0, %1\n\t"
"csrw pmpcfg0, %0\n\t"
".align 2\n\t"
"1:"
: : "r" (pmpc), "r" (pmpa) : "t0");

// set up supervisor trap handling
write_csr(stvec, pa2kva(trap_entry));
write_csr(sscratch, pa2kva(read_csr(mscratch)));
write_csr(medeleg,
(1 << CAUSE_USER_ECALL) |
(1 << CAUSE_FETCH_PAGE_FAULT) |
(1 << CAUSE_LOAD_PAGE_FAULT) |
(1 << CAUSE_STORE_PAGE_FAULT));
//write_csr(stvec, pa2kva(trap_entry));
//write_csr(sscratch, pa2kva(read_csr(mscratch)));
//write_csr(medeleg,
// (1 << CAUSE_USER_ECALL) |
// (1 << CAUSE_FETCH_PAGE_FAULT) |
// (1 << CAUSE_LOAD_PAGE_FAULT) |
// (1 << CAUSE_STORE_PAGE_FAULT));
// FPU on; accelerator on; allow supervisor access to user memory access
write_csr(mstatus, MSTATUS_FS | MSTATUS_XS);
write_csr(mie, 0);

random = 1 + (random % MAX_TEST_PAGES);
freelist_head = pa2kva((void*)&freelist_nodes[0]);
freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]);
freelist_head = ((void*)&freelist_nodes[0]);
freelist_tail = (&freelist_nodes[MAX_TEST_PAGES-1]);
for (long i = 0; i < MAX_TEST_PAGES; i++)
{
freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE;
freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]);
freelist_nodes[i].addr = DRAM_BASE + MEGAPAGE_SIZE + random*PGSIZE;
freelist_nodes[i].next = (&freelist_nodes[i+1]);
random = LFSR_NEXT(random);
}
freelist_nodes[MAX_TEST_PAGES-1].next = 0;
Expand Down
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