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Updated PT, modified V and added VT. #1
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iihihiuh
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0d85d04
Adding blackparrot termination conditions
dpetrisko 24cf46c
changed V env to use M mode instead of S
farzamgl 1c0b36c
added fake ufinish CSR for simulation end
farzamgl 1423706
Adding link to our mtvec handler
dpetrisko 0a3d6bc
Simplifying termination condition
dpetrisko 1a8e080
functions incorporated
14428d0
start point
79cb643
timer environment add
2109241
macro applyed
27542f1
revert v
e6a8f25
macro name changed unncessary constant removed
37fde77
backup file removed
46293c3
v in bp_mode recovered
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Why are you changing PIE here?
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on mret. mie in mstatus will become mpie in mstatus. mie in mstatus is the global interrupt enable signal.
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That’s done in hardware
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Yes. If I do not write MPIE before mret, MIE will be clearer after mret.
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No it won’t. On the timer interrupt, MPIE becomes MIE (1) in hardware. On MRET, MIE becomes MPIE (1)
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Because on MRET, MIE becomes MPIE. I write MPIE to 1 to before MRET to enable timer interrupt after MRE.
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You’re not understanding. MPIE is already 1 when you’re in the trap. If it weren’t, you wouldn’t have taken the trap
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Look at how the old spike code worked. They didn’t need to write to MPIE
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This MPIE is only for initialization. During reset mstatus was all zeros.