Feature: re-enable non-halting RTT on a few targets

src/target/cortexm.c

@@ -48,9 +48,16 @@
 #include <assert.h>
 
 static bool cortexm_vector_catch(target_s *target, int argc, const char **argv);
+#ifdef ENABLE_RTT
+static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv);
+#include "rtt.h"
+#endif
 
 const command_s cortexm_cmd_list[] = {
 	{"vector_catch", cortexm_vector_catch, "Catch exception vectors"},
+#ifdef ENABLE_RTT
+	{"mem_nohalt", cortexm_mem_nohalt, "Toggle halting during memory accesses (affects RTT)"},
+#endif
 	{NULL, NULL, NULL},
 };
 
@@ -1269,6 +1276,31 @@ static bool cortexm_vector_catch(target_s *target, int argc, const char **argv)
 	return true;
 }
 
+#ifdef ENABLE_RTT
+static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv)
+{
+	bool enable = false;
+	if (argc > 2) {
+		tc_printf(target, "Usage: monitor mem_nohalt <enable|disable>");
+		return false;
+	}
+	if ((argc == 2) && parse_enable_or_disable(argv[1], &enable)) {
+		if (enable)
+			target->target_options |= TOPT_NON_HALTING_MEM_IO;
+		else
+			target->target_options &= ~TOPT_NON_HALTING_MEM_IO;
+		/* Force reapplying halt settings in rtt.c */
+		rtt_found = false;
+
+		return true;
+	}
+	tc_printf(target, "Target allows non-halting memory IO: %s\n",
+		target->target_options & TOPT_NON_HALTING_MEM_IO ? "yes" : "no");
+	return true;
+}
+
+#endif
+
 static bool cortexm_hostio_request(target_s *const target)
 {
 	/* Read out the information from the target needed to complete the request */

src/target/nrf51.c

@@ -144,6 +144,8 @@ bool nrf51_probe(target_s *t)
 		uint32_t ram_size = target_mem32_read32(t, NRF52_INFO_RAM);
 		t->driver = "nRF52";
 		t->target_options |= TOPT_INHIBIT_NRST;
+		/* On nRF52 SoC, Cortex-M4F allows SRAM access without halting */
+		t->target_options |= TOPT_NON_HALTING_MEM_IO;
 		target_add_ram32(t, 0x20000000U, ram_size * 1024U);
 		nrf51_add_flash(t, 0, page_size * code_size, page_size);
 		nrf51_add_flash(t, NRF51_UICR, page_size, page_size);

src/target/stm32f1.c

@@ -286,8 +286,10 @@ bool gd32f1_probe(target_s *target)
 	switch (device_id) {
 	case 0x414U: /* GD32F30x_HD, High density */
 	case 0x430U: /* GD32F30x_XD, XL-density */
-		target->driver = "GD32F3";
+		target->driver = "GD32F3 HD/XD";
 		block_size = 0x800;
+		/* On this SoC, Cortex-M4F allows SRAM access without halting */
+		target->target_options |= TOPT_NON_HALTING_MEM_IO;
 		break;
 	case 0x418U: /* Connectivity Line */
 		target->driver = "GD32F2";
@@ -297,14 +299,19 @@ bool gd32f1_probe(target_s *target)
 		if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) == CORTEX_M23)
 			target->driver = "GD32E230"; /* GD32E230, 64 KiB max in 1 KiB pages */
 		else if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) == CORTEX_M4) {
-			target->driver = "GD32F3";
+			target->driver = "GD32F3 MD";
 			block_size = 0x800;
-		} else
+		} else {
 			target->driver = "GD32F1"; /* GD32F103, 1 KiB pages */
+			/* On this SoC, Cortex-M3 allows SRAM access without halting */
+			target->target_options |= TOPT_NON_HALTING_MEM_IO;
+		}
 		break;
 	case 0x444U: /* GD32E50x_CL, 512 KiB max in 8 KiB pages */
 		target->driver = "GD32E5";
 		block_size = 0x2000;
+		/* On this SoC, Cortex-M33 allows SRAM access without halting */
+		target->target_options |= TOPT_NON_HALTING_MEM_IO;
 		break;
 	default:
 		return false;
@@ -494,6 +501,8 @@ static bool at32f403a_407_detect(target_s *target, const uint16_t part_id)
 	}
 	// All parts have 96 KiB SRAM
 	target_add_ram32(target, STM32F1_SRAM_BASE, 96U * 1024U);
+	/* On AT32F403A/F407 SoC, Cortex-M4F allows SRAM access without halting */
+	target->target_options |= TOPT_NON_HALTING_MEM_IO;
 	target->driver = "AT32F403A/407";
 	target->part_id = part_id;
 	target->target_options |= STM32F1_TOPT_32BIT_WRITES;
@@ -1008,6 +1017,9 @@ bool stm32f1_probe(target_s *target)
 	stm32f1_add_flash(target, STM32F1_FLASH_BANK1_BASE, flash_size, block_size);
 	target_add_commands(target, stm32f1_cmd_list, target->driver);
 
+	/* On STM32F1 (F3, F0) SoC, Cortex-M3 (M4F, M0) allows SRAM access without halting */
+	target->target_options |= TOPT_NON_HALTING_MEM_IO;
+
 	/* Now we have a stable debug environment, make sure the WDTs + WFI and WFE instructions can't cause problems */
 	return stm32f1_configure_dbgmcu(target, dbgmcu_config_taddr);
 }

src/target/stm32f4.c

@@ -441,6 +441,10 @@ static bool stm32f4_attach(target_s *const target)
 		}
 	}
 
+	/* On STM32F4 SoC, Cortex-M4F allows SRAM access without halting */
+	if (!is_f7 && target->part_id != ID_STM32F20X)
+		target->target_options |= TOPT_NON_HALTING_MEM_IO;
+
 	/* Now we have a base RAM map, rebuild the Flash map */
 	uint8_t split = 0;
 	uint32_t bank_length;

src/target/stm32g0.c

@@ -299,6 +299,9 @@ bool stm32g0_probe(target_s *target)
 		return false;
 
 	target_add_ram32(target, RAM_START, ram_size);
+	/* On this SoC, Cortex-M0+ allows SRAM access without halting */
+	target->target_options |= TOPT_NON_HALTING_MEM_IO;
+
 	/* Even dual Flash bank devices have a contiguous Flash memory space */
 	stm32g0_add_flash(target, FLASH_START, flash_size, FLASH_PAGE_SIZE);
 

src/target/stm32l4.c

@@ -847,6 +847,10 @@ static bool stm32l4_attach(target_s *const target)
 	} else
 		stm32l4_add_flash(target, STM32L4_FLASH_BANK_1_BASE, flash_len * 1024U, 0x800, UINT32_MAX);
 
+	/* On STM32G47x SoC, Cortex-M4F allows SRAM access without halting */
+	if (device->device_id == ID_STM32G47)
+		target->target_options |= TOPT_NON_HALTING_MEM_IO;
+
 	/* Clear all errors in the status register. */
 	stm32l4_flash_write32(target, FLASH_SR, stm32l4_flash_read32(target, FLASH_SR));
 	return true;