Toaplan Version 1 FPGA Implemenation for MiSTerFPGA
FPGA compatible core for Toaplan Version 1 arcade hardware for MiSTerFPGA written by Darren Olafson. This core is based on Zero Wing and will be verified against physical hardware (Out Zone/Zero Wing Conversion).
This FPGA compatible core is in active development with assistance from 𝕓𝕝𝕒𝕔𝕜𝕨𝕚𝕟𝕖 and atrac17. Physical hardware on loan from @owlnonymous.
| Game | Status | Released |
|---|---|---|
| Zero Wing | Implemented | Pending |
| Out Zone (Zero Wing TP-015 PCB conversion) | Implemented | Pending |
| Out Zone | Ongoing | No |
| Hellfire | Implemented | Pending |
| Truxton | Ongoing | No |
| Vimana | Ongoing | No |
| Fire Shark | Ongoing | No |
| Rally Bike | Ongoing | No |
| Demon's World | FPGA Implementation slated by Jotego | N/A |
-Screen Flip/Cocktail Mode has yet to be implemented
-Exiting the service menu hangs on a sound error
-Clock domains need to be verified
-Sprites disappearing when they touch the first scanline or first pixel of a scanline (Out Zone)
-OPL2 sound implementation (W.I.P)
-HD647180X sound implementation (Fire Shark / Vimana)
FPGA core timings will be taken from Out Zone (Zero Wing TP-015 PCB conversion) on loan courtesy of @owlnonymous. More information to follow.
Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached.