Add lab materials for cores

cores/VeerEH1/Makefile

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+# SPDX-License-Identifier: Apache-2.0
+# Copyright 2020 Western Digital Corporation or its affiliates.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+RV_ROOT = /home/bouncmpe/cores/VeerEH1
+CONF_PARAMS = -set iccm_enable
+TEST_CFLAGS = -g -O3 -funroll-all-loops
+ABI = -mabi=ilp32 -march=rv32im
+
+# Allow snapshot override
+target = default
+snapshot = $(target)
+
+# Allow tool override
+VEER_CONFIG = ${RV_ROOT}/configs/veer.config
+IRUN = xrun
+VCS = vcs
+VERILATOR = verilator
+VLOG = qverilog
+RIVIERA = riviera
+GCC_PREFIX = riscv64-unknown-elf
+BUILD_DIR = snapshots/${snapshot}
+TBDIR = ${RV_ROOT}/testbench
+
+# Define default test name
+TEST = hello_world
+
+# Define default test directory
+TEST_DIR = /workspaces/labs344/programs
+HEX_DIR = $(TBDIR)/hex
+ifneq (,$(wildcard $(TBDIR)/tests/$(TEST)))
+        TEST_DIR = $(TBDIR)/tests/$(TEST)
+endif
+
+# provide specific link file
+ifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))
+	LINK = $(TBDIR)/link.ld
+else
+	LINK = $(TEST_DIR)/$(TEST).ld
+endif
+
+OFILES = $(TEST).o
+
+-include $(TEST_DIR)/$(TEST).mki
+
+VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)
+TBFILES = $(TBDIR)/tb_top.sv $(TBDIR)/ahb_sif.sv
+
+defines = $(BUILD_DIR)/common_defines.vh ${RV_ROOT}/design/include/veer_types.sv
+includes = -I${RV_ROOT}/design/include -I${RV_ROOT}/design/lib  -I${BUILD_DIR}
+
+# Verilator supports only C++14 and newer
+CFLAGS += -std=c++17
+
+# Optimization for better performance; alternative is nothing for
+# slower runtime (faster compiles) -O2 for faster runtime (slower
+# compiles), or -O for balance.
+VERILATOR_MAKE_FLAGS = OPT_FAST="-O3"
+
+# Targets
+all: clean verilator
+
+clean:
+	rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots veer* \
+	verilator* *.elf obj* *.o ucli.key vc_hdrs.h csrc *.csv \
+	work dataset.asdb  library.cfg
+
+# If define files do not exist, then run veer.config.
+${BUILD_DIR}/defines.h :
+	BUILD_PATH=${BUILD_DIR} ${VEER_CONFIG} -target=$(target) $(CONF_PARAMS)
+
+##################### Verilog Builds #####################################
+
+verilator-build: ${TBFILES} ${BUILD_DIR}/defines.h test_tb_top.cpp
+	echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
+	RV_ROOT=${RV_ROOT} $(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
+                -Wno-UNOPTFLAT \
+                -I${RV_ROOT}/testbench \
+				-f ${RV_ROOT}/testbench/flist \
+                ${TBFILES} \
+                --top-module tb_top -exe test_tb_top.cpp \
+				--autoflush --timing --trace --timescale 1ns/100ps
+	cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir
+	$(MAKE) -j -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)
+	touch verilator-build
+
+##################### Simulation Runs #####################################
+
+verilator: program.hex verilator-build
+	timeout 1s "./obj_dir/Vtb_top"
+
+##################### Test Build #####################################
+
+program.hex: $(OFILES) $(LINK)
+	@echo Building $(TEST)
+	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(TEST).map -T$(LINK) -o $(TEST).elf -nostdlib $(OFILES) $(TEST_LIBS)
+	$(GCC_PREFIX)-objcopy -O verilog $(TEST).elf program.hex
+	$(GCC_PREFIX)-objdump -S  $(TEST).elf > $(TEST).dis
+	@echo Completed building $(TEST)
+
+%.o : %.s ${BUILD_DIR}/defines.h
+	$(GCC_PREFIX)-cpp -I${BUILD_DIR}  $<  > $*.cpp.s
+	$(GCC_PREFIX)-as $(ABI) $*.cpp.s -o $@
+
+
+%.o : %.c ${BUILD_DIR}/defines.h
+	$(GCC_PREFIX)-gcc -I${BUILD_DIR} ${TEST_CFLAGS} ${ABI} -nostdlib -c $< -o $@
+
+view:
+	gtkwave sim.vcd -T default_wave.tcl
+
+.PHONY: clean verilator view

cores/VeerEL2/Makefile

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+# SPDX-License-Identifier: Apache-2.0
+# Copyright 2020 Western Digital Corporation or its affiliates.
+# Copyright 2024 Antmicro <www.antmicro.com>
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+RV_ROOT = /home/bouncmpe/cores/VeerEL2
+TEST_CFLAGS = -g -gdwarf -O3 -funroll-all-loops
+ABI = -mabi=ilp32
+LD_ABI = $(ABI) -march=rv32im
+
+# Allow snapshot override
+target = default
+snapshot = $(target)
+
+# Allow tool override
+VEER_CONFIG = ${RV_ROOT}/configs/veer.config
+VERILATOR = verilator
+GCC_PREFIX = riscv64-unknown-elf
+BUILD_DIR = snapshots/${snapshot}
+TBDIR = ${RV_ROOT}/testbench
+
+# Override march depending on used GCC version
+ifneq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)
+	GCCVERSIONGT11 := $(shell expr `$(GCC_PREFIX)-gcc -dumpversion | cut -f1 -d.` \>= 11)
+	ifeq "$(GCCVERSIONGT11)" "1"
+		CC_ABI = $(ABI) -march=rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs;
+	else
+		CC_ABI = $(ABI) -march=rv32im
+	endif
+endif
+
+VERILATOR_SKIP_WARNINGS = -Wno-IMPLICITSTATIC -Wno-TIMESCALEMOD -Wno-ASCRANGE \
+	-Wno-CASEINCOMPLETE -Wno-INITIALDLY -Wno-WIDTH -Wno-UNOPTFLAT
+
+# Define test name
+TEST = hello_world
+TEST_DIR = /workspaces/labs344/programs
+HEX_DIR = ${TBDIR}/hex
+OFILES = $(TEST).o
+
+ifdef assert
+ ASSERT_DEFINES = +define+RV_ASSERT_ON
+endif
+
+# provide specific link file
+ifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))
+	LINK = $(BUILD_DIR)/link.ld
+else
+	LINK = $(TEST_DIR)/$(TEST).ld
+endif
+
+VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)
+
+-include $(TEST_DIR)/$(TEST).mki
+
+# Testbench DPI sources
+TB_DPI_SRCS = jtagdpi/jtagdpi.c \
+              tcp_server/tcp_server.c
+
+TB_DPI_INCS := $(addprefix -I$(TBDIR)/,$(dir $(TB_DPI_SRCS)))
+# Add testbench include paths
+CFLAGS += $(TB_DPI_INCS)
+
+TB_DPI_SRCS := $(addprefix $(TBDIR)/,$(TB_DPI_SRCS))
+
+# Testbench sources
+TB_VERILATOR_SRCS = $(TBDIR)/test_tb_top.cpp $(TB_DPI_SRCS)
+
+TBFILES = $(TBDIR)/tb_top_pkg.sv \
+          $(TBDIR)/tb_top.sv \
+          $(TBDIR)/ahb_sif.sv \
+          $(TBDIR)/jtagdpi/jtagdpi.sv \
+          $(TBDIR)/ahb_lite_2to1_mux.sv
+
+defines  = $(BUILD_DIR)/common_defines.vh
+defines += ${RV_ROOT}/design/include/el2_def.sv
+defines += $(BUILD_DIR)/el2_pdef.vh
+includes = -I${BUILD_DIR} -I$(TBDIR)/axi4_mux
+
+# Verilator supports only C++14 and newer
+CFLAGS += -std=c++17
+
+# Optimization for better performance; alternative is nothing for
+# slower runtime (faster compiles) -O2 for faster runtime (slower
+# compiles), or -O for balance.
+VERILATOR_MAKE_FLAGS = OPT_FAST="-O3"
+
+# Targets
+all: clean verilator
+
+clean:
+	rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots veer* \
+	verilator* *.elf obj* *.o *.sym ucli.key vc_hdrs.h csrc *.csv work \
+	dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb
+
+############ Model Builds ###############################
+
+# If define files do not exist, then run veer.config.
+${BUILD_DIR}/defines.h:
+	BUILD_PATH=${BUILD_DIR} ${RV_ROOT}/configs/veer.config -target=$(target) $(CONF_PARAMS)
+
+verilator-build: ${TBFILES} ${BUILD_DIR}/defines.h $(TB_VERILATOR_SRCS)
+	RV_ROOT=${RV_ROOT} $(VERILATOR)  --cc -CFLAGS "${CFLAGS}" $(defines) \
+	  $(includes) -I${RV_ROOT}/testbench -f ${RV_ROOT}/testbench/flist \
+	  $(VERILATOR_SKIP_WARNINGS) ${TBFILES} --top-module tb_top \
+	  -exe $(TB_VERILATOR_SRCS) --autoflush --timing --trace --timescale 1ns/100ps
+	cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir/
+	$(MAKE) -e -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)
+	touch verilator-build
+
+############ TEST Simulation ###############################
+
+verilator: program.hex verilator-build
+	timeout 1s "./obj_dir/Vtb_top"
+
+############ TEST build ###############################
+
+program.hex: $(OFILES) ${BUILD_DIR}/defines.h
+	@echo Building $(TEST)
+	$(GCC_PREFIX)-gcc $(LD_ABI) --verbose -Wl,-Map=$(TEST).map -T$(LINK) $(TEST_LIBS) -nostdlib $(OFILES) -o $(TEST).elf
+	$(GCC_PREFIX)-objcopy -O verilog  $(TEST).elf program.hex
+	$(GCC_PREFIX)-objdump -S  $(TEST).elf > $(TEST).dis
+	$(GCC_PREFIX)-nm -B -n $(TEST).elf > $(TEST).sym
+	@echo Completed building $(TEST)
+
+%.o : %.s ${BUILD_DIR}/defines.h
+	$(GCC_PREFIX)-cpp -I${BUILD_DIR}  $<  > $*.cpp.s
+	$(GCC_PREFIX)-as ${CC_ABI} $*.cpp.s -o $@
+
+%.o : %.c ${BUILD_DIR}/defines.h
+	$(GCC_PREFIX)-gcc ${includes} ${TEST_CFLAGS} -DCOMPILER_FLAGS="\"${TEST_CFLAGS}\"" ${CC_ABI} -c $< -o $@
+
+view:
+	gtkwave sim.vcd -T default_wave.tcl
+
+.PHONY: clean verilator view
+

cores/VeerEL2/default_wave.tcl

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+gtkwave::setZoomFactor -12
+gtkwave::setWindowStartTime 0
+
+gtkwave::addSignalsFromList core_clk
+
+gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.ifu.ifc_fetch_addr_f
+gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.ifu.ifu_fetch_data_f
+gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.dec.dec_i0_instr_d
+gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.dec.decode.i0_inst_x
+gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.dec.decode.i0_inst_r
+
+# gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.exu.i_alu.pc_in;          # PC input to ALU
+# gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.exu.i_alu.a_in;           # First input to ALU
+# gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.exu.i_alu.b_in;           # Second input to ALU
+# gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.exu.i_alu.result;         # ALU result
+
+# gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.exu.exu_flush_final
+# gtkwave::addSignalsFromList tb_top.rvtop_wrapper.rvtop.veer.exu.exu_flush_path_final

programs/addmul.s

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+#include "defines.h"
+
+.globl _start
+_start:
+
+# Enable Caches in MRAC
+li x1, 0x5f555555
+csrw 0x7c0, x1
+
+# Disable Pipeling
+# Setting the first bit of the 0x7F9 register to 1 disables the pipeline
+# https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/docs/source/core-control.md
+# li t2, 0x001
+# csrrs t1, 0x7F9, t2
+
+# Disable Advanced Branch Predictor
+# Setting the third bit of the 0x7F9 register to 1 disables the branch predictor
+# https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/docs/source/core-control.md
+# li t2, 0x008
+# csrrs t1, 0x7F9, t2
+
+li x28, 0x1
+li x29, 0x2
+li x30, 0x4
+li x31, 0x1
+
+REPEAT:
+   nop;
+   nop;
+   mul x28, x29, x29
+   add x30, x30, x31
+   nop; 
+   nop; 
+   nop; 
+   nop;
+   add x29, x29, 1
+   nop; 
+   nop; 
+   nop; 
+   nop;
+   beq  zero, zero, REPEAT # Repeat the loop

programs/arithmetic.s

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+#include "defines.h"
+
+.global _start
+_start:
+
+// Clear minstret (Instruction Retired Register)
+csrw minstret, zero
+csrw minstreth, zero
+
+// Enable Caches in MRAC
+li x1, 0x5f555555
+csrw 0x7c0, x1
+
+# Register t3 is also called register 28 (x28)
+li t3, 0x0					# t3 = 0
+
+REPEAT:
+	addi t3, t3, 6			# t3 = t3 + 6
+	addi t3, t3, -1		    # t3 = t3 - 1
+	andi t3, t3, 3			# t3 = t3 AND 3
+	beq  zero, zero, REPEAT	# Repeat the loop
+
+.end