Enable checker and cleanup.

calonso88 · Apr 13, 2024 · 22d4697 · 22d4697
1 parent 3246849
commit 22d4697
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Showing 2 changed files with 10 additions and 10 deletions.
diff --git a/src/rsa_control.sv b/src/rsa_control.sv
@@ -29,13 +29,13 @@ module rsa_control #(parameter int WIDTH = 8) (rstb, clk, ena, clear, E, clear_m
   logic load_exp;
   logic shift_exp;
 
-  logic [($clog2(WIDTH-1))-1:0] counter_steps; // [3:0]
-  logic [($clog2(WIDTH-1))-1:0] counter_rounds; // [3:0]
+  logic [($clog2(WIDTH-1))-1:0] counter_steps;
+  logic [($clog2(WIDTH-1))-1:0] counter_rounds;
   logic clear_counter_steps;
   logic clear_counter_rounds;
   logic increment_steps;
   logic increment_rounds;
-  logic [($clog2(WIDTH-1))-1:0] const_counter_compare; // [3:0]
+  logic [($clog2(WIDTH-1))-1:0] const_counter_compare;
 
   // FSM states type
   typedef enum logic [3:0] {
@@ -186,7 +186,7 @@ module rsa_control #(parameter int WIDTH = 8) (rstb, clk, ena, clear, E, clear_m
         clear_counter_rounds = 1'b0;
         increment_steps = 1'b1;
         increment_rounds = 1'b0;
-        if ( counter_steps == const_counter_compare ) begin // 4'd10
+        if ( counter_steps == const_counter_compare ) begin
           next_state = STATE_POST_MAP;
         end else begin
           next_state = STATE_MAP;
@@ -247,7 +247,7 @@ module rsa_control #(parameter int WIDTH = 8) (rstb, clk, ena, clear, E, clear_m
         clear_counter_rounds = 1'b0;
         increment_steps = 1'b1;
         increment_rounds = 1'b0;
-        if ( counter_steps == const_counter_compare ) begin // 4'd10
+        if ( counter_steps == const_counter_compare ) begin
           next_state = STATE_POST_MMM;
         end else begin
           next_state = STATE_MMM;
@@ -270,7 +270,7 @@ module rsa_control #(parameter int WIDTH = 8) (rstb, clk, ena, clear, E, clear_m
         clear_counter_rounds = 1'b0;
         increment_steps = 1'b0;
         increment_rounds = 1'b1;
-        if ( counter_rounds == const_counter_compare ) begin // 4'd10
+        if ( counter_rounds == const_counter_compare ) begin
           next_state = STATE_PRE_REMAP;
         end else begin
           next_state = STATE_PRE_MMM;
@@ -312,7 +312,7 @@ module rsa_control #(parameter int WIDTH = 8) (rstb, clk, ena, clear, E, clear_m
         clear_counter_rounds = 1'b0;
         increment_steps = 1'b1;
         increment_rounds = 1'b0;
-        if ( counter_steps == const_counter_compare ) begin // 4'd10
+        if ( counter_steps == const_counter_compare ) begin
           next_state = POST_REMAP;
         end else begin
           next_state = STATE_REMAP;

diff --git a/test/test.py b/test/test.py
@@ -290,9 +290,9 @@ async def test_spi(dut):
     d = pow(e, -1, phi_m)
 
     # Number of bits for RSA implementation
+    hwbits = bits + 2
     # DEBUG
-    hwbits = 8 + 2
-    ####################hwbits = bits + 2
+    #hwbits = 8 + 2
     # DEBUG
 
     # Montgomery constant
@@ -341,7 +341,7 @@ async def test_spi(dut):
 
     assert plain_text == decrypted_text
     # DEBUG
-    #assert encrypted_text_design == encrypted_text 
+    assert encrypted_text_design == encrypted_text 
     # DEBUG
 
     # Write reg[0] = 0xF0