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`timescale 1ns / 1ps | ||
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module processing_element_mux (mi, bi, mbi, ai, qi, mux_out); | ||
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input mi, bi, mbi, ai, qi; | ||
output mux_out; | ||
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reg mux_out; | ||
wire [1:0] mux_sel; | ||
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assign mux_sel = {ai, qi}; | ||
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always @(mbi or bi or mi or mux_sel) begin | ||
case (mux_sel) | ||
2'b11 : mux_out = mbi; | ||
2'b10 : mux_out = bi; | ||
2'b01 : mux_out = mi; | ||
2'b00 : mux_out = 1'b0; | ||
default mux_out = 1'b0; | ||
endcase | ||
end | ||
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endmodule |