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Issues list

Math Stress Test enhancement New feature or request help wanted Extra attention is needed
#56 opened Feb 20, 2025 by PythonLinks
Olimex board overheating question Further information is requested
#55 opened Feb 19, 2025 by tarik-ibrahimovic
YOSYS synth_gatemate netlist not compatible with p_r blocking Critical. Blocking further progress bug Something isn't working
#54 opened Feb 14, 2025 by tarik-ibrahimovic
LUTRAM stress test underutilization question Further information is requested
#52 opened Feb 14, 2025 by tarik-ibrahimovic
Installation Error good first issue Good for newcomers
#50 opened Dec 21, 2024 by udge2022
One and only EU
#49 opened Dec 12, 2024 by goran-mahovlic
IP Request: PCIE Gen2 EndPoint Phase2 For ideas and proposals to consider in the next funding round.
#47 opened Dec 7, 2024 by chili-chips-ba
PCB PMOD Request: Olimex connector to dual DVI-IN/DVI-OUT (ddvIO) Assembled Boad is assembled PCB request Phase2 For ideas and proposals to consider in the next funding round.
#46 opened Dec 5, 2024 by goran-mahovlic
Constraints-driven P_R?! question Further information is requested
#38 opened Sep 27, 2024 by chili-chips-ba
L2T4 logic funcion gaps compared to standard LUT4?! question Further information is requested
#37 opened Sep 27, 2024 by chili-chips-ba
Out of context / Virtual Pin Support enhancement New feature or request
#34 opened Sep 12, 2024 by JulianKemmerer
WANTED: IOSERDES for GateMate enhancement New feature or request
#33 opened Sep 7, 2024 by chili-chips-ba
No warning issued for unconstrained ports enhancement New feature or request
#31 opened Aug 20, 2024 by tarik-ibrahimovic
Mismatch in post-PnR sim and chip operation blocking Critical. Blocking further progress bug Something isn't working help wanted Extra attention is needed
#30 opened Aug 18, 2024 by tarik-ibrahimovic
Undefined behavior in synthesis depending on the bit width of variables blocking Critical. Blocking further progress bug Something isn't working
#25 opened Jul 22, 2024 by tarik-ibrahimovic
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