Add initial DCLS support and documentation #246

kgugala · 2024-10-14T18:11:30Z

No description provided.

github-actions · 2024-10-14T18:12:37Z

design/el2_veer_lockstep.sv

+      .scan_mode(scan_mode)
+  );
+
+assign corruption_detected = 0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign corruption_detected = 0;

assign corruption_detected = 0;

github-actions · 2024-10-14T18:12:41Z

design/el2_veer_lockstep.sv

+    input logic o_cpu_halt_ack,  // Core Acknowledge to Halt request
+    input logic o_cpu_halt_status,  // 1'b1 indicates processor is halted
+    input logic o_cpu_run_ack,  // Core Acknowledge to run request
+    input logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 168 [Style: line-length] [line-length]

github-actions · 2024-10-14T18:12:41Z

design/el2_veer_lockstep.sv

+    input logic                          ic_rd_en,
+
+    input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data,  // Data to fill to the Icache. With ECC
+    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]

github-actions · 2024-10-14T18:12:41Z

design/el2_veer_lockstep.sv

+
+    input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data,  // Data to fill to the Icache. With ECC
+    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 132 [Style: line-length] [line-length]

github-actions · 2024-10-15T12:47:28Z

Links to coverage and verification reports for this PR (#246) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-15T23:50:21Z

Links to coverage and verification reports for this PR (#246) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-22T15:13:33Z

design/lib/el2_regfile_if.sv

+  );
+
+  modport veer_tlu_rf(
+      output pc, npc, mstatus, mie, mtvec, mscratch, mepc, mcause, mtval, mip, mcyclel, mcycleh, minstretl, minstreth, mrac


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]

github-actions · 2024-10-22T15:13:33Z

design/lib/el2_regfile_if.sv

+
+  modport veer_rf_src(
+      output ra, sp, fp, a0, a1, a2, a3, a4, a5, a6, a7,
+      output pc, npc, mstatus, mie, mtvec, mscratch, mepc, mcause, mtval, mip, mcyclel, mcycleh, minstretl, minstreth, mrac


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]

github-actions · 2024-10-22T15:13:33Z

design/lib/el2_regfile_if.sv

+
+  modport veer_rf_sink(
+      input ra, sp, fp, a0, a1, a2, a3, a4, a5, a6, a7,
+      input pc, npc, mstatus, mie, mtvec, mscratch, mepc, mcause, mtval, mip, mcyclel, mcycleh, minstretl, minstreth, mrac


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 122 [Style: line-length] [line-length]

github-actions · 2024-10-22T15:13:52Z

design/dec/el2_dec.sv

+      el2_regfile_if regfile_if ();
+      assign regfile.ra = regfile_if.ra;
+      assign regfile.sp = regfile_if.sp;
+      assign regfile.fp = regfile_if.fp;
+      assign regfile.a0 = regfile_if.a0;
+      assign regfile.a1 = regfile_if.a1;
+      assign regfile.a2 = regfile_if.a2;
+      assign regfile.a3 = regfile_if.a3;
+      assign regfile.a4 = regfile_if.a4;
+      assign regfile.a5 = regfile_if.a5;
+      assign regfile.a6 = regfile_if.a6;
+      assign regfile.a7 = regfile_if.a7;
+
+      assign regfile.pc        = regfile_if.pc;
+      assign regfile.npc       = regfile_if.npc;
+      assign regfile.mstatus   = regfile_if.mstatus;
+      assign regfile.mie       = regfile_if.mie;
+      assign regfile.mtvec     = regfile_if.mtvec;
+      assign regfile.mscratch  = regfile_if.mscratch;
+      assign regfile.mepc      = regfile_if.mepc;
+      assign regfile.mcause    = regfile_if.mcause;
+      assign regfile.mtval     = regfile_if.mtval;
+      assign regfile.mip       = regfile_if.mip;
+      assign regfile.mcyclel   = regfile_if.mcyclel;
+      assign regfile.mcycleh   = regfile_if.mcycleh;
+      assign regfile.minstretl = regfile_if.minstretl;
+      assign regfile.minstreth = regfile_if.minstreth;
+      assign regfile.mrac      = regfile_if.mrac;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

el2_regfile_if regfile_if ();

assign regfile.ra = regfile_if.ra;

assign regfile.sp = regfile_if.sp;

assign regfile.fp = regfile_if.fp;

assign regfile.a0 = regfile_if.a0;

assign regfile.a1 = regfile_if.a1;

assign regfile.a2 = regfile_if.a2;

assign regfile.a3 = regfile_if.a3;

assign regfile.a4 = regfile_if.a4;

assign regfile.a5 = regfile_if.a5;

assign regfile.a6 = regfile_if.a6;

assign regfile.a7 = regfile_if.a7;

assign regfile.pc = regfile_if.pc;

assign regfile.npc = regfile_if.npc;

assign regfile.mstatus = regfile_if.mstatus;

assign regfile.mie = regfile_if.mie;

assign regfile.mtvec = regfile_if.mtvec;

assign regfile.mscratch = regfile_if.mscratch;

assign regfile.mepc = regfile_if.mepc;

assign regfile.mcause = regfile_if.mcause;

assign regfile.mtval = regfile_if.mtval;

assign regfile.mip = regfile_if.mip;

assign regfile.mcyclel = regfile_if.mcyclel;

assign regfile.mcycleh = regfile_if.mcycleh;

assign regfile.minstretl = regfile_if.minstretl;

assign regfile.minstreth = regfile_if.minstreth;

assign regfile.mrac = regfile_if.mrac;

el2_regfile_if regfile_if ();

assign regfile.ra = regfile_if.ra;

assign regfile.sp = regfile_if.sp;

assign regfile.fp = regfile_if.fp;

assign regfile.a0 = regfile_if.a0;

assign regfile.a1 = regfile_if.a1;

assign regfile.a2 = regfile_if.a2;

assign regfile.a3 = regfile_if.a3;

assign regfile.a4 = regfile_if.a4;

assign regfile.a5 = regfile_if.a5;

assign regfile.a6 = regfile_if.a6;

assign regfile.a7 = regfile_if.a7;

assign regfile.pc = regfile_if.pc;

assign regfile.npc = regfile_if.npc;

assign regfile.mstatus = regfile_if.mstatus;

assign regfile.mie = regfile_if.mie;

assign regfile.mtvec = regfile_if.mtvec;

assign regfile.mscratch = regfile_if.mscratch;

assign regfile.mepc = regfile_if.mepc;

assign regfile.mcause = regfile_if.mcause;

assign regfile.mtval = regfile_if.mtval;

assign regfile.mip = regfile_if.mip;

assign regfile.mcyclel = regfile_if.mcyclel;

assign regfile.mcycleh = regfile_if.mcycleh;

assign regfile.minstretl = regfile_if.minstretl;

assign regfile.minstreth = regfile_if.minstreth;

assign regfile.mrac = regfile_if.mrac;

github-actions · 2024-10-22T15:13:53Z

design/dec/el2_dec.sv


-  el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
+  el2_dec_tlu_ctl #(.pt(pt)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

el2_dec_tlu_ctl #(.pt(pt)

el2_dec_tlu_ctl #(

.pt(pt)

github-actions · 2024-10-22T15:13:53Z

design/dec/el2_dec.sv

+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+      .regfile(regfile_if.veer_tlu_rf),
+`endif
+      .*);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.*);

.*

);

github-actions · 2024-10-22T15:13:53Z

design/dec/el2_dec.sv

      .raddr0(dec_i0_rs1_d[4:0]),
      .raddr1(dec_i0_rs2_d[4:0]),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.raddr0(dec_i0_rs1_d[4:0]),

.raddr1(dec_i0_rs2_d[4:0]),

.raddr0 (dec_i0_rs1_d[4:0]),

.raddr1 (dec_i0_rs2_d[4:0]),

github-actions · 2024-10-22T15:13:53Z

design/dec/el2_dec_gpr_ctl.sv

@@ -39,6 +39,10 @@ import el2_pkg::*;
    output logic [31:0] rd0,         // read data


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [31:0] rd0, // read data

output logic [31:0] rd0, // read data

github-actions · 2024-10-22T15:13:54Z

design/el2_veer_wrapper.sv

+   el2_regfile_if regfile ();
+   // TODO: Connect to the Shadow Core
+   initial begin
+      $display("Dual Core Lockstep enabled!\n");
+   end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

el2_regfile_if regfile ();

// TODO: Connect to the Shadow Core

initial begin

$display("Dual Core Lockstep enabled!\n");

end

el2_regfile_if regfile ();

// TODO: Connect to the Shadow Core

initial begin

$display("Dual Core Lockstep enabled!\n");

end

github-actions · 2024-10-22T15:13:54Z

design/el2_veer_wrapper.sv

   // Instantiate the el2_veer core
   el2_veer #(.pt(pt)) veer (
                                .clk(clk),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Instantiate the el2_veer core

el2_veer #(.pt(pt)) veer (

.clk(clk),

// Instantiate the el2_veer core

el2_veer #(

.pt(pt)

) veer (

.clk(clk),

github-actions · 2024-10-22T15:13:54Z

design/el2_veer_wrapper.sv

   // Instantiate the el2_veer core
   el2_veer #(.pt(pt)) veer (
                                .clk(clk),
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+                                .regfile(regfile.veer_rf_src),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.regfile(regfile.veer_rf_src),

.regfile(regfile.veer_rf_src),

github-actions · 2024-10-22T15:13:54Z

design/lib/el2_regfile_if.sv

+  logic [31:0] ra; // Return address
+  logic [31:0] sp; // Stack pointer
+  logic [31:0] fp; // Frame pointer
+  logic [31:0] a0, a1; // Function arguments 0-1 / Return values 0-1
+  logic [31:0] a2, a3, a4, a5, a6, a7; // Function arguments 2-7


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [31:0] ra; // Return address

logic [31:0] sp; // Stack pointer

logic [31:0] fp; // Frame pointer

logic [31:0] a0, a1; // Function arguments 0-1 / Return values 0-1

logic [31:0] a2, a3, a4, a5, a6, a7; // Function arguments 2-7

logic [31:0] ra; // Return address

logic [31:0] sp; // Stack pointer

logic [31:0] fp; // Frame pointer

logic [31:0] a0, a1; // Function arguments 0-1 / Return values 0-1

logic [31:0] a2, a3, a4, a5, a6, a7; // Function arguments 2-7

github-actions · 2024-10-22T15:13:54Z

design/lib/el2_regfile_if.sv

+  logic [31:0] pc, npc; // (Next) Program Counter
+  logic [31:0] mstatus; // Machine status
+  logic [31:0] mie; // Machine interrupt enable
+  logic [31:0] mtvec; // Machine trap-handler base address
+  logic [31:0] mscratch; // Scratch register for machine trap handlers
+  logic [31:0] mepc; // Machine exception program counter
+  logic [31:0] mcause; // Machine trap cause
+  logic [31:0] mtval; // Machine bad address or instruction
+  logic [31:0] mip; // Machine interrupt pending
+  logic [31:0] mcyclel; // Machine cycle counter
+  logic [31:0] mcycleh; // Machine cycle counter
+  logic [31:0] minstretl; // Machine instructions-retired counter
+  logic [31:0] minstreth; // Machine instructions-retired counter
+  logic [31:0] mrac; // Region access control
+
+  modport veer_gpr_rf(
+      output ra, sp, fp, a0, a1, a2, a3, a4, a5, a6, a7
+  );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [31:0] pc, npc; // (Next) Program Counter

logic [31:0] mstatus; // Machine status

logic [31:0] mie; // Machine interrupt enable

logic [31:0] mtvec; // Machine trap-handler base address

logic [31:0] mscratch; // Scratch register for machine trap handlers

logic [31:0] mepc; // Machine exception program counter

logic [31:0] mcause; // Machine trap cause

logic [31:0] mtval; // Machine bad address or instruction

logic [31:0] mip; // Machine interrupt pending

logic [31:0] mcyclel; // Machine cycle counter

logic [31:0] mcycleh; // Machine cycle counter

logic [31:0] minstretl; // Machine instructions-retired counter

logic [31:0] minstreth; // Machine instructions-retired counter

logic [31:0] mrac; // Region access control

modport veer_gpr_rf(

output ra, sp, fp, a0, a1, a2, a3, a4, a5, a6, a7

);

logic [31:0] pc, npc; // (Next) Program Counter

logic [31:0] mstatus; // Machine status

logic [31:0] mie; // Machine interrupt enable

logic [31:0] mtvec; // Machine trap-handler base address

logic [31:0] mscratch; // Scratch register for machine trap handlers

logic [31:0] mepc; // Machine exception program counter

logic [31:0] mcause; // Machine trap cause

logic [31:0] mtval; // Machine bad address or instruction

logic [31:0] mip; // Machine interrupt pending

logic [31:0] mcyclel; // Machine cycle counter

logic [31:0] mcycleh; // Machine cycle counter

logic [31:0] minstretl; // Machine instructions-retired counter

logic [31:0] minstreth; // Machine instructions-retired counter

logic [31:0] mrac; // Region access control

modport veer_gpr_rf(output ra, sp, fp, a0, a1, a2, a3, a4, a5, a6, a7);

github-actions · 2024-10-22T17:16:44Z

Links to coverage and verification reports for this PR (#246) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-10-25T16:36:47Z

design/dec/el2_dec.sv

+      el2_regfile_if regfile_if ();
+      assign regfile.gpr.ra = regfile_if.gpr.ra;
+      assign regfile.gpr.sp = regfile_if.gpr.sp;
+      assign regfile.gpr.fp = regfile_if.gpr.fp;
+      assign regfile.gpr.a0 = regfile_if.gpr.a0;
+      assign regfile.gpr.a1 = regfile_if.gpr.a1;
+      assign regfile.gpr.a2 = regfile_if.gpr.a2;
+      assign regfile.gpr.a3 = regfile_if.gpr.a3;
+      assign regfile.gpr.a4 = regfile_if.gpr.a4;
+      assign regfile.gpr.a5 = regfile_if.gpr.a5;
+      assign regfile.gpr.a6 = regfile_if.gpr.a6;
+      assign regfile.gpr.a7 = regfile_if.gpr.a7;
+
+      assign regfile.tlu.pc        = regfile_if.tlu.pc;
+      assign regfile.tlu.npc       = regfile_if.tlu.npc;
+      assign regfile.tlu.mstatus   = regfile_if.tlu.mstatus;
+      assign regfile.tlu.mie       = regfile_if.tlu.mie;
+      assign regfile.tlu.mtvec     = regfile_if.tlu.mtvec;
+      assign regfile.tlu.mscratch  = regfile_if.tlu.mscratch;
+      assign regfile.tlu.mepc      = regfile_if.tlu.mepc;
+      assign regfile.tlu.mcause    = regfile_if.tlu.mcause;
+      assign regfile.tlu.mtval     = regfile_if.tlu.mtval;
+      assign regfile.tlu.mip       = regfile_if.tlu.mip;
+      assign regfile.tlu.mcyclel   = regfile_if.tlu.mcyclel;
+      assign regfile.tlu.mcycleh   = regfile_if.tlu.mcycleh;
+      assign regfile.tlu.minstretl = regfile_if.tlu.minstretl;
+      assign regfile.tlu.minstreth = regfile_if.tlu.minstreth;
+      assign regfile.tlu.mrac      = regfile_if.tlu.mrac;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

el2_regfile_if regfile_if ();

assign regfile.gpr.ra = regfile_if.gpr.ra;

assign regfile.gpr.sp = regfile_if.gpr.sp;

assign regfile.gpr.fp = regfile_if.gpr.fp;

assign regfile.gpr.a0 = regfile_if.gpr.a0;

assign regfile.gpr.a1 = regfile_if.gpr.a1;

assign regfile.gpr.a2 = regfile_if.gpr.a2;

assign regfile.gpr.a3 = regfile_if.gpr.a3;

assign regfile.gpr.a4 = regfile_if.gpr.a4;

assign regfile.gpr.a5 = regfile_if.gpr.a5;

assign regfile.gpr.a6 = regfile_if.gpr.a6;

assign regfile.gpr.a7 = regfile_if.gpr.a7;

assign regfile.tlu.pc = regfile_if.tlu.pc;

assign regfile.tlu.npc = regfile_if.tlu.npc;

assign regfile.tlu.mstatus = regfile_if.tlu.mstatus;

assign regfile.tlu.mie = regfile_if.tlu.mie;

assign regfile.tlu.mtvec = regfile_if.tlu.mtvec;

assign regfile.tlu.mscratch = regfile_if.tlu.mscratch;

assign regfile.tlu.mepc = regfile_if.tlu.mepc;

assign regfile.tlu.mcause = regfile_if.tlu.mcause;

assign regfile.tlu.mtval = regfile_if.tlu.mtval;

assign regfile.tlu.mip = regfile_if.tlu.mip;

assign regfile.tlu.mcyclel = regfile_if.tlu.mcyclel;

assign regfile.tlu.mcycleh = regfile_if.tlu.mcycleh;

assign regfile.tlu.minstretl = regfile_if.tlu.minstretl;

assign regfile.tlu.minstreth = regfile_if.tlu.minstreth;

assign regfile.tlu.mrac = regfile_if.tlu.mrac;

el2_regfile_if regfile_if ();

assign regfile.gpr.ra = regfile_if.gpr.ra;

assign regfile.gpr.sp = regfile_if.gpr.sp;

assign regfile.gpr.fp = regfile_if.gpr.fp;

assign regfile.gpr.a0 = regfile_if.gpr.a0;

assign regfile.gpr.a1 = regfile_if.gpr.a1;

assign regfile.gpr.a2 = regfile_if.gpr.a2;

assign regfile.gpr.a3 = regfile_if.gpr.a3;

assign regfile.gpr.a4 = regfile_if.gpr.a4;

assign regfile.gpr.a5 = regfile_if.gpr.a5;

assign regfile.gpr.a6 = regfile_if.gpr.a6;

assign regfile.gpr.a7 = regfile_if.gpr.a7;

assign regfile.tlu.pc = regfile_if.tlu.pc;

assign regfile.tlu.npc = regfile_if.tlu.npc;

assign regfile.tlu.mstatus = regfile_if.tlu.mstatus;

assign regfile.tlu.mie = regfile_if.tlu.mie;

assign regfile.tlu.mtvec = regfile_if.tlu.mtvec;

assign regfile.tlu.mscratch = regfile_if.tlu.mscratch;

assign regfile.tlu.mepc = regfile_if.tlu.mepc;

assign regfile.tlu.mcause = regfile_if.tlu.mcause;

assign regfile.tlu.mtval = regfile_if.tlu.mtval;

assign regfile.tlu.mip = regfile_if.tlu.mip;

assign regfile.tlu.mcyclel = regfile_if.tlu.mcyclel;

assign regfile.tlu.mcycleh = regfile_if.tlu.mcycleh;

assign regfile.tlu.minstretl = regfile_if.tlu.minstretl;

assign regfile.tlu.minstreth = regfile_if.tlu.minstreth;

assign regfile.tlu.mrac = regfile_if.tlu.mrac;

github-actions · 2024-10-25T16:36:47Z

design/dec/el2_dec_gpr_ctl.sv

+   assign regfile.gpr.ra = gpr_out[1][31:0]; // x1
+   assign regfile.gpr.sp = gpr_out[2][31:0]; // x2
+   assign regfile.gpr.fp = gpr_out[8][31:0]; // x8
+   assign regfile.gpr.a0 = gpr_out[10][31:0]; // x10
+   assign regfile.gpr.a1 = gpr_out[11][31:0]; // x11
+   assign regfile.gpr.a2 = gpr_out[12][31:0]; // x12
+   assign regfile.gpr.a3 = gpr_out[13][31:0]; // x13
+   assign regfile.gpr.a4 = gpr_out[14][31:0]; // x14
+   assign regfile.gpr.a5 = gpr_out[15][31:0]; // x15
+   assign regfile.gpr.a6 = gpr_out[16][31:0]; // x16
+   assign regfile.gpr.a7 = gpr_out[17][31:0]; // x17


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign regfile.gpr.ra = gpr_out[1][31:0]; // x1

assign regfile.gpr.sp = gpr_out[2][31:0]; // x2

assign regfile.gpr.fp = gpr_out[8][31:0]; // x8

assign regfile.gpr.a0 = gpr_out[10][31:0]; // x10

assign regfile.gpr.a1 = gpr_out[11][31:0]; // x11

assign regfile.gpr.a2 = gpr_out[12][31:0]; // x12

assign regfile.gpr.a3 = gpr_out[13][31:0]; // x13

assign regfile.gpr.a4 = gpr_out[14][31:0]; // x14

assign regfile.gpr.a5 = gpr_out[15][31:0]; // x15

assign regfile.gpr.a6 = gpr_out[16][31:0]; // x16

assign regfile.gpr.a7 = gpr_out[17][31:0]; // x17

assign regfile.gpr.ra = gpr_out[1][31:0]; // x1

assign regfile.gpr.sp = gpr_out[2][31:0]; // x2

assign regfile.gpr.fp = gpr_out[8][31:0]; // x8

assign regfile.gpr.a0 = gpr_out[10][31:0]; // x10

assign regfile.gpr.a1 = gpr_out[11][31:0]; // x11

assign regfile.gpr.a2 = gpr_out[12][31:0]; // x12

assign regfile.gpr.a3 = gpr_out[13][31:0]; // x13

assign regfile.gpr.a4 = gpr_out[14][31:0]; // x14

assign regfile.gpr.a5 = gpr_out[15][31:0]; // x15

assign regfile.gpr.a6 = gpr_out[16][31:0]; // x16

assign regfile.gpr.a7 = gpr_out[17][31:0]; // x17

github-actions · 2024-10-25T16:36:47Z

design/el2_veer_lockstep.sv

+          delayed_main_core_regfile[i+1].gpr <= '0;
+          delayed_main_core_regfile[i+1].tlu <= '0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

delayed_main_core_regfile[i+1].gpr <= '0;

delayed_main_core_regfile[i+1].tlu <= '0;

delayed_main_core_regfile[i+1].gpr <= '0;

delayed_main_core_regfile[i+1].tlu <= '0;

github-actions · 2024-10-25T16:36:48Z

design/el2_veer_wrapper.sv

+                                .*
+                                );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.*

);

.*

);

github-actions · 2024-10-25T16:36:48Z

design/el2_veer_wrapper.sv

+                                );
+
+`ifdef RV_LOCKSTEP_ENABLE
+   logic lockstep_corruption_detected;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic lockstep_corruption_detected;

logic lockstep_corruption_detected;

github-actions · 2024-10-25T16:36:50Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [              31:0] lsu_axi_awaddr;
+  logic [               3:0] lsu_axi_awregion;
+  logic [               7:0] lsu_axi_awlen;
+  logic [               2:0] lsu_axi_awsize;
+  logic [               1:0] lsu_axi_awburst;
+  logic                      lsu_axi_awlock;
+  logic [               3:0] lsu_axi_awcache;
+  logic [               2:0] lsu_axi_awprot;
+  logic [               3:0] lsu_axi_awqos;
+
+  logic        lsu_axi_wvalid;
+  logic        lsu_axi_wready;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 31:0] lsu_axi_awaddr;

logic [ 3:0] lsu_axi_awregion;

logic [ 7:0] lsu_axi_awlen;

logic [ 2:0] lsu_axi_awsize;

logic [ 1:0] lsu_axi_awburst;

logic lsu_axi_awlock;

logic [ 3:0] lsu_axi_awcache;

logic [ 2:0] lsu_axi_awprot;

logic [ 3:0] lsu_axi_awqos;

logic lsu_axi_wvalid;

logic lsu_axi_wready;

logic [31:0] lsu_axi_awaddr;

logic [3:0] lsu_axi_awregion;

logic [7:0] lsu_axi_awlen;

logic [2:0] lsu_axi_awsize;

logic [1:0] lsu_axi_awburst;

logic lsu_axi_awlock;

logic [3:0] lsu_axi_awcache;

logic [2:0] lsu_axi_awprot;

logic [3:0] lsu_axi_awqos;

logic lsu_axi_wvalid;

logic lsu_axi_wready;

github-actions · 2024-10-25T16:36:50Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [ 7:0] lsu_axi_wstrb;
+  logic        lsu_axi_wlast;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 7:0] lsu_axi_wstrb;

logic lsu_axi_wlast;

logic [7:0] lsu_axi_wstrb;

logic lsu_axi_wlast;

github-actions · 2024-10-25T16:36:51Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic                      lsu_axi_bvalid;
+  logic                      lsu_axi_bready;
+  logic [               1:0] lsu_axi_bresp;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic lsu_axi_bvalid;

logic lsu_axi_bready;

logic [ 1:0] lsu_axi_bresp;

logic lsu_axi_bvalid;

logic lsu_axi_bready;

logic [1:0] lsu_axi_bresp;

github-actions · 2024-10-25T16:36:51Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+   // AXI Read Channels
+  logic                      lsu_axi_arvalid;
+  logic                      lsu_axi_arready;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// AXI Read Channels

logic lsu_axi_arvalid;

logic lsu_axi_arready;

// AXI Read Channels

logic lsu_axi_arvalid;

logic lsu_axi_arready;

github-actions · 2024-10-25T16:36:51Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [              31:0] lsu_axi_araddr;
+  logic [               3:0] lsu_axi_arregion;
+  logic [               7:0] lsu_axi_arlen;
+  logic [               2:0] lsu_axi_arsize;
+  logic [               1:0] lsu_axi_arburst;
+  logic                      lsu_axi_arlock;
+  logic [               3:0] lsu_axi_arcache;
+  logic [               2:0] lsu_axi_arprot;
+  logic [               3:0] lsu_axi_arqos;
+
+  logic                      lsu_axi_rvalid;
+  logic                      lsu_axi_rready;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 31:0] lsu_axi_araddr;

logic [ 3:0] lsu_axi_arregion;

logic [ 7:0] lsu_axi_arlen;

logic [ 2:0] lsu_axi_arsize;

logic [ 1:0] lsu_axi_arburst;

logic lsu_axi_arlock;

logic [ 3:0] lsu_axi_arcache;

logic [ 2:0] lsu_axi_arprot;

logic [ 3:0] lsu_axi_arqos;

logic lsu_axi_rvalid;

logic lsu_axi_rready;

logic [31:0] lsu_axi_araddr;

logic [3:0] lsu_axi_arregion;

logic [7:0] lsu_axi_arlen;

logic [2:0] lsu_axi_arsize;

logic [1:0] lsu_axi_arburst;

logic lsu_axi_arlock;

logic [3:0] lsu_axi_arcache;

logic [2:0] lsu_axi_arprot;

logic [3:0] lsu_axi_arqos;

logic lsu_axi_rvalid;

logic lsu_axi_rready;

github-actions · 2024-10-25T16:37:09Z

design/el2_veer_lockstep.sv

+      delayed_main_core_regfile[0].tlu <= main_core_regfile.tlu;
+    end
+  end
+  for (genvar i = 0; i < LockstepDelay; i++) begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2024-10-25T16:37:10Z

design/el2_veer_lockstep.sv

+
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+  logic regfile_corrupted;
+  assign regfile_corrupted   = (delayed_main_core_regfile[LockstepDelay].gpr != shadow_core_regfile.gpr)


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]

github-actions · 2024-10-25T16:37:10Z

design/el2_veer_lockstep.sv

+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+  logic regfile_corrupted;
+  assign regfile_corrupted   = (delayed_main_core_regfile[LockstepDelay].gpr != shadow_core_regfile.gpr)
+                             | (delayed_main_core_regfile[LockstepDelay].tlu != shadow_core_regfile.tlu);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]

Internal-tag: [#62496] Signed-off-by: Michal Czyz <[email protected]> Signed-off-by: Wiktoria Kuna <[email protected]>

Internal-tag: [#66891] Signed-off-by: Wiktoria Kuna <[email protected]>

Signed-off-by: Robert Szczepanski <[email protected]>

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

verification/block/dcls/el2_veer_lockstep_wrapper.sv|356|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|359|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|367|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|373|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|383|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|386|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|390|
verification/block/dcls/el2_veer_lockstep_wrapper.sv|392|

github-actions · 2024-10-25T16:55:26Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [              63:0] lsu_axi_rdata;
+  logic [               1:0] lsu_axi_rresp;
+  logic                      lsu_axi_rlast;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 63:0] lsu_axi_rdata;

logic [ 1:0] lsu_axi_rresp;

logic lsu_axi_rlast;

logic [63:0] lsu_axi_rdata;

logic [1:0] lsu_axi_rresp;

logic lsu_axi_rlast;

github-actions · 2024-10-25T16:55:26Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic                      ifu_axi_awvalid;
+  logic                      ifu_axi_awready;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic ifu_axi_awvalid;

logic ifu_axi_awready;

logic ifu_axi_awvalid;

logic ifu_axi_awready;

github-actions · 2024-10-25T16:55:26Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [              31:0] ifu_axi_awaddr;
+  logic [               3:0] ifu_axi_awregion;
+  logic [               7:0] ifu_axi_awlen;
+  logic [               2:0] ifu_axi_awsize;
+  logic [               1:0] ifu_axi_awburst;
+  logic                      ifu_axi_awlock;
+  logic [               3:0] ifu_axi_awcache;
+  logic [               2:0] ifu_axi_awprot;
+  logic [               3:0] ifu_axi_awqos;
+
+  logic        ifu_axi_wvalid;
+  logic        ifu_axi_wready;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 31:0] ifu_axi_awaddr;

logic [ 3:0] ifu_axi_awregion;

logic [ 7:0] ifu_axi_awlen;

logic [ 2:0] ifu_axi_awsize;

logic [ 1:0] ifu_axi_awburst;

logic ifu_axi_awlock;

logic [ 3:0] ifu_axi_awcache;

logic [ 2:0] ifu_axi_awprot;

logic [ 3:0] ifu_axi_awqos;

logic ifu_axi_wvalid;

logic ifu_axi_wready;

logic [31:0] ifu_axi_awaddr;

logic [3:0] ifu_axi_awregion;

logic [7:0] ifu_axi_awlen;

logic [2:0] ifu_axi_awsize;

logic [1:0] ifu_axi_awburst;

logic ifu_axi_awlock;

logic [3:0] ifu_axi_awcache;

logic [2:0] ifu_axi_awprot;

logic [3:0] ifu_axi_awqos;

logic ifu_axi_wvalid;

logic ifu_axi_wready;

github-actions · 2024-10-25T16:55:26Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [ 7:0] ifu_axi_wstrb;
+  logic        ifu_axi_wlast;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 7:0] ifu_axi_wstrb;

logic ifu_axi_wlast;

logic [7:0] ifu_axi_wstrb;

logic ifu_axi_wlast;

github-actions · 2024-10-25T16:55:26Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic                      ifu_axi_bvalid;
+  logic                      ifu_axi_bready;
+  logic [               1:0] ifu_axi_bresp;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic ifu_axi_bvalid;

logic ifu_axi_bready;

logic [ 1:0] ifu_axi_bresp;

logic ifu_axi_bvalid;

logic ifu_axi_bready;

logic [1:0] ifu_axi_bresp;

github-actions · 2024-10-25T16:55:29Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic        lsu_hready;
+  logic        lsu_hresp;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic lsu_hready;

logic lsu_hresp;

logic lsu_hready;

logic lsu_hresp;

github-actions · 2024-10-25T16:55:29Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [ 2:0] sb_hburst;
+  logic        sb_hmastlock;
+  logic [ 3:0] sb_hprot;
+  logic [ 2:0] sb_hsize;
+  logic [ 1:0] sb_htrans;
+  logic        sb_hwrite;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 2:0] sb_hburst;

logic sb_hmastlock;

logic [ 3:0] sb_hprot;

logic [ 2:0] sb_hsize;

logic [ 1:0] sb_htrans;

logic sb_hwrite;

logic [2:0] sb_hburst;

logic sb_hmastlock;

logic [3:0] sb_hprot;

logic [2:0] sb_hsize;

logic [1:0] sb_htrans;

logic sb_hwrite;

github-actions · 2024-10-25T16:55:29Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic        sb_hready;
+  logic        sb_hresp;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic sb_hready;

logic sb_hresp;

logic sb_hready;

logic sb_hresp;

github-actions · 2024-10-25T16:55:29Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+   // DMA Slave
+  logic        dma_hsel;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// DMA Slave

logic dma_hsel;

// DMA Slave

logic dma_hsel;

github-actions · 2024-10-25T16:55:29Z

verification/block/dcls/el2_veer_lockstep_wrapper.sv

+  logic [ 2:0] dma_hburst;
+  logic        dma_hmastlock;
+  logic [ 3:0] dma_hprot;
+  logic [ 2:0] dma_hsize;
+  logic [ 1:0] dma_htrans;
+  logic        dma_hwrite;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [ 2:0] dma_hburst;

logic dma_hmastlock;

logic [ 3:0] dma_hprot;

logic [ 2:0] dma_hsize;

logic [ 1:0] dma_htrans;

logic dma_hwrite;

logic [2:0] dma_hburst;

logic dma_hmastlock;

logic [3:0] dma_hprot;

logic [2:0] dma_hsize;

logic [1:0] dma_htrans;

logic dma_hwrite;

github-actions · 2024-10-25T18:43:14Z

Links to coverage and verification reports for this PR (#246) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions bot reviewed Oct 14, 2024

View reviewed changes

mgielda changed the title ~~Add DCLS support~~ Add initial DCLS support and documentation Oct 14, 2024

kgugala force-pushed the dcls branch from 7702769 to 9f5a5f4 Compare October 15, 2024 18:27

tmichalak force-pushed the dcls branch from 9f5a5f4 to 1642e83 Compare October 17, 2024 11:44

github-actions bot reviewed Oct 22, 2024

View reviewed changes

github-actions bot reviewed Oct 25, 2024

View reviewed changes

mczyz-antmicro and others added 8 commits October 25, 2024 18:47

Draft lockstep implementation

8a29cfe

Internal-tag: [#62496] Signed-off-by: Michal Czyz <[email protected]> Signed-off-by: Wiktoria Kuna <[email protected]>

Docs: Add DCLS documentation draft

15108f7

Internal-tag: [#66891] Signed-off-by: Wiktoria Kuna <[email protected]>

Expose VeeR register file to top level

16e7b21

Signed-off-by: Robert Szczepanski <[email protected]>

Add config options for Dual Core Lockstep (DCLS)

b9e824c

Signed-off-by: Robert Szczepanski <[email protected]>

Fix simulation build for VCS

58edf36

Signed-off-by: Robert Szczepanski <[email protected]>

Refactor register file interface to ease signal assignments

9e239a0

Signed-off-by: Robert Szczepanski <[email protected]>

Improve lockstep connections and detection mechanism

292b341

Signed-off-by: Robert Szczepanski <[email protected]>

Add proper reset test for DCLS

8b6a64e

Signed-off-by: Robert Szczepanski <[email protected]>

tmichalak force-pushed the dcls branch from fc0b68c to 8b6a64e Compare October 25, 2024 16:54

github-actions bot reviewed Oct 25, 2024

View reviewed changes

	assign corruption_detected = 0;
	assign corruption_detected = 0;


		el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
		el2_dec_tlu_ctl #(.pt(pt)

		@@ -39,6 +39,10 @@ import el2_pkg::*;
		output logic [31:0] rd0, // read data

	.regfile(regfile.veer_rf_src),
	.regfile(regfile.veer_rf_src),

		delayed_main_core_regfile[i+1].gpr <= '0;
		delayed_main_core_regfile[i+1].tlu <= '0;

-                                .*
-                                );
+      .*
+  );

	logic lockstep_corruption_detected;
	logic lockstep_corruption_detected;

Add initial DCLS support and documentation #246

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Add initial DCLS support and documentation #246

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