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Add PatternWithEnumTypeInNestedModule #590

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@RRozak RRozak commented Nov 10, 2021

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typedef struct packed {
logic [2:0] a;
logic [1:0] b;
} struct_ab;

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Struct names have to ends with _t [Style: struct-union-conventions] [struct-union-name-style]

typedef struct packed {
logic [1:0] a;
logic [2:0] b;
} struct_ab;

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Struct names have to ends with _t [Style: struct-union-conventions] [struct-union-name-style]

Signed-off-by: Ryszard Różak <[email protected]>
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RRozak commented Nov 10, 2021

It waits for chipsalliance/Surelog#2183

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RRozak commented Nov 19, 2021

It still doesn't work.

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RRozak commented Dec 15, 2021

It gives warning top.sv:22:15: Operator PATMEMBER expects 3 bits on the Pattern value, but Pattern value's CONST '2'h3' generates 2 bits.

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