Adds list of metadata for verification failures

[BrendenPage]

Each set of dut.v and gold.v in tests/bsg/bsg_micro_designs_results that did not pass verification is provided with a small metadata file detailing some select information regarding its reasons for failure.

Matching Results dictates the section of verification dedicated to matching the ports together between the two instances, whereas Verification Results dictates the section that determines the logical equivalence of compare points.

If a Verification Results section is empty but there is still a provided file, that means that the failure was due to a mismatched set of ports and the design could not be verified. Fixing it at the matching level is likely to fix these issues.

A table of the different types of compare points is given here:
BBNet: multiply-driven net
BBox: black-box
BBPin: black-box pin
Block: hierarchical block
BlPin: hierarchical block pin
Cut: cut-point
DFF: non-constant DFF register
DFF0: constant 0 DFF register
DFF1: constant 1 DFF register
DFFX: constant X DFF register
DFF0X: constrained 0X DFF register
DFF1X: constrained 1X DFF register
LAT: non-constant latch register
LAT0: constant 0 latch register
LAT1: constant 1 latch register
LATX: constant X latch register
LAT0X: constrained 0X latch register
LAT1X: constrained 1X latch register
LATCG: clock-gating latch register
TLA: transparent latch register
TLA0X: transparent constrained 0X latch register
TLA1X: transparent constrained 1X latch register
Loop: cycle break point
Net: matchable net
Port: primary (top-level) port
Und: undriven signal cut-point
Unk: unknown signal cut-point

[BrendenPage]

New push has the run data for the set of dut.v files generated by this PR with the files located at this link. There are several files for which dut.v files have been created but were not previously present with the gold.v files. I am unable to run the diff on these files as I do not have information on the parameters that generated these files.

@mglb @alaindargelas

bsg_assembler_in.json
bsg_assembler_out.json
bsg_binary_plus_one_to_gray.json
bsg_counting_leading_zeros.json
bsg_fpu_clz.json
bsg_fpu_i2f.json
bsg_fpu_sticky.json
bsg_round_robin_fifo_to_fifo.json
bsg_unconcentrate_static.json

[mglb]

We've updated the CI to generate parameters.txt files containing parameter values used for generating dut.v files.
PR: chipsalliance/synlig#1794
CI run: https://github.com/antmicro/yosys-systemverilog/actions/runs/5322046201
Direct link to output files: https://github.com/antmicro/yosys-systemverilog/suites/13729263278/artifacts/759995417