Add ISA extension when Zmmul

Signed-off-by: kanataso <[email protected]>
chipsalliance · Jul 10, 2023 · b8c5cef · b8c5cef
1 parent 78e8d28
commit b8c5cef
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
@@ -112,6 +112,7 @@ trait HasNonDiplomaticTileParameters {
       //Some(Seq("zicntr")) ++
       Option.when(tileParams.core.useConditionalZero)(Seq("zicond")) ++
       Some(Seq("zicsr", "zifencei", "zihpm")) ++
+      Option.when(tileParams.core.mulDiv.nonEmpty && !tileParams.core.mulDiv.get.divEnabled)(Seq("zmmul")) ++
       Option.when(tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen >= 16 && tileParams.core.fpu.get.minFLen <= 16)(Seq("zfh")) ++
       Option.when(tileParams.core.useBitManip)(Seq("zba", "zbb", "zbc")) ++
       Option.when(tileParams.core.hasBitManipCrypto)(Seq("zbkb", "zbkc", "zbkx")) ++