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Update Instructions with riscv-opcodes #2972

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merged 4 commits into from
May 6, 2022
Merged

Update Instructions with riscv-opcodes #2972

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9edd2d8
Instructions: sync from riscv-opcodes
ZenithalHourlyRate May 3, 2022
1bc5e01
Fix Instructions32 since riscv-opcodes API change
ZenithalHourlyRate May 4, 2022
c301881
Fix legacy instruction name
ZenithalHourlyRate May 3, 2022
55e4222
CustomInstructions: Add RoCC Instructions
ZenithalHourlyRate May 3, 2022
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4 changes: 2 additions & 2 deletions src/main/scala/rocket/CSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -813,8 +813,8 @@ class CSRFile(

val system_insn = io.rw.cmd === CSR.I
val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU)
val decode_table = Seq( SCALL-> List(Y,N,N,N,N,N,N,N,N),
SBREAK-> List(N,Y,N,N,N,N,N,N,N),
val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N),
EBREAK-> List(N,Y,N,N,N,N,N,N,N),
MRET-> List(N,N,Y,N,N,N,N,N,N),
CEASE-> List(N,N,N,Y,N,N,N,N,N),
WFI-> List(N,N,N,N,Y,N,N,N,N)) ++
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24 changes: 24 additions & 0 deletions src/main/scala/rocket/CustomInstructions.scala
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Expand Up @@ -10,6 +10,30 @@ object CustomInstructions {
def CEASE = BitPat("b00110000010100000000000001110011")
def CFLUSH_D_L1 = BitPat("b111111000000?????000000001110011")
def CDISCARD_D_L1 = BitPat("b111111000010?????000000001110011")
def CUSTOM0 = BitPat("b?????????????????000?????0001011")
def CUSTOM0_RS1 = BitPat("b?????????????????010?????0001011")
def CUSTOM0_RS1_RS2 = BitPat("b?????????????????011?????0001011")
def CUSTOM0_RD = BitPat("b?????????????????100?????0001011")
def CUSTOM0_RD_RS1 = BitPat("b?????????????????110?????0001011")
def CUSTOM0_RD_RS1_RS2 = BitPat("b?????????????????111?????0001011")
def CUSTOM1 = BitPat("b?????????????????000?????0101011")
def CUSTOM1_RS1 = BitPat("b?????????????????010?????0101011")
def CUSTOM1_RS1_RS2 = BitPat("b?????????????????011?????0101011")
def CUSTOM1_RD = BitPat("b?????????????????100?????0101011")
def CUSTOM1_RD_RS1 = BitPat("b?????????????????110?????0101011")
def CUSTOM1_RD_RS1_RS2 = BitPat("b?????????????????111?????0101011")
def CUSTOM2 = BitPat("b?????????????????000?????1011011")
def CUSTOM2_RS1 = BitPat("b?????????????????010?????1011011")
def CUSTOM2_RS1_RS2 = BitPat("b?????????????????011?????1011011")
def CUSTOM2_RD = BitPat("b?????????????????100?????1011011")
def CUSTOM2_RD_RS1 = BitPat("b?????????????????110?????1011011")
def CUSTOM2_RD_RS1_RS2 = BitPat("b?????????????????111?????1011011")
def CUSTOM3 = BitPat("b?????????????????000?????1111011")
def CUSTOM3_RS1 = BitPat("b?????????????????010?????1111011")
def CUSTOM3_RS1_RS2 = BitPat("b?????????????????011?????1111011")
def CUSTOM3_RD = BitPat("b?????????????????100?????1111011")
def CUSTOM3_RD_RS1 = BitPat("b?????????????????110?????1111011")
def CUSTOM3_RD_RS1_RS2 = BitPat("b?????????????????111?????1111011")
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}

object CustomCSRs {
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/Frontend.scala
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Expand Up @@ -223,7 +223,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
val rviCall = (rviJALR || rviJump) && rviBits(7)
val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
val rvcJAL = Bool(xLen == 32) && bits === Instructions.C_JAL
val rvcJAL = Bool(xLen == 32) && bits === Instructions32.C_JAL
val rvcJump = bits === Instructions.C_J || rvcJAL
val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen).bImm.asSInt, new RVCDecoder(bits, xLen).jImm.asSInt)
val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0
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17 changes: 10 additions & 7 deletions src/main/scala/rocket/IDecode.scala
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Expand Up @@ -111,8 +111,8 @@ class IDecode(implicit val p: Parameters) extends DecodeConstants

FENCE-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N),

SCALL-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
SBREAK-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
ECALL-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
EBREAK-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
MRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
WFI-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
CEASE-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
Expand Down Expand Up @@ -190,9 +190,12 @@ class NMIDecode(implicit val p: Parameters) extends DecodeConstants
class I32Decode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
SLLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
SRLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
SRAI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
Instructions32.SLLI->
List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
Instructions32.SRLI->
List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
Instructions32.SRAI->
List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
}

class I64Decode(implicit val p: Parameters) extends DecodeConstants
Expand Down Expand Up @@ -337,13 +340,13 @@ class FDecode(implicit val p: Parameters) extends DecodeConstants
FNMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
FCLASS_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
FMV_X_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
FMV_X_W-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
FEQ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
FLT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
FLE_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
FMV_S_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
FMV_W_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
FLW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
Expand Down
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