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@sequencer sequencer released this 16 Sep 02:40
· 886 commits to master since this release
v1.4
a7b016e
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Rocket

  • [CSR] add vcsr and move vxrm/vxstat from fcsr to that register set (#2400, #2422)
  • [CSR] disallow writes to MSTATUS.XS (#2508)
  • [CSR] expand TracedInstruction.cause to xLen (#2548)
  • [CSR][mstatus] implement updated MPRV from priv-1.12 (#2206)
  • [CSR] add `mcountinhibit from priv-1.11 (#2693)
    • ignore PAUSE when mcountinhibit(0) === 1 (#2700)
  • [CSR] Comply with priv spec by resetting and initializing mcause to 0 (#2333)
  • [events] add SuperscalarEventSets (#2337, #2506)
  • [events] make fields public for tapping signals (#2464, #2524)
  • [i$] fix ccover bug to cover all beats of D channel corruption #2755
  • [d$] updates
    • fix elaboration with < 4 MiB of physical address space (#2367)
    • guarantee no-alloc accesses are ordered even if aliased (#2358)
    • [ecc] fixed a rare bug where under the right conditions stores to the same word resulted in one store detecting an error while the other does not (#2458)
    • [HellaCache] introduce subWordBits param to support subbanking (#2645)
    • support specifying cache index when aliasing is possible (#2697, #2730)
    • reduce latency on inclusion and coherence misses by allowing D$ to voluntarily release (aka "noisy drop") cache lines (#2696)
      • follow-up to fix deadlock (#2714)
      • follow-up to fix performance (#2739)
  • distinguish a supervisor mode that does not use MMU/VM (#2422, #2499)
  • [hartid]
    • fixed an issue where the Rocket core's placement would be impacted by non-constant hartid (#2432)
    • add a diplomatic node for assigning hartid (#2447)
  • [Replacement][PseudoLRU] fix performance issue with PseudoLRU for replacements when number of ways is not a power of 2 (#2493, #2498)
  • [Replacement][d$] configure replacement policy with parameter to indicate wheteher policy is used on a per-set basis or a global basis (#2656)
  • [PTW]
    • replace round robin arbitration with static arbitration (#2433)
    • fixed a bug where an L2TLB write would almost always block the next L2TLB search when MMU and clock gating were enabled (#2601)
    • wait for L2TLB to refill before searching (#2619)
    • [PTWPerfEvents] add (unused) Performance Monitor Events for L2TLB hit and PTE Cache Miss/Hit (#2668, #2688, #2692)
    • enable configurable set-associtive L2 TLB (#2748, #2753)
      • default configuration is direct-mapped
  • enable Sv48 setting page levels equal to 4 (#2434)
  • [PMP] remove NA4 coverpoint for pmp granularity > 4 (#2625)
  • [TLB]
    • check PutPartial support separately from PutFull (#2503)
    • fix a rare refill/invalidate race condition (#2534)
    • configure L1 D/I TLBs by set, entry, and replacement policy (#2574, #2621)
    • add params nTLBBasePageSectors and nTLBSuperpages for both I and D TLBs #2595
  • [CoreMonitor]
    • add privilege mode and exception signals (#2387)
    • now prints only retired instructions (#2372)
    • separate wren into wrenx/wrenf for integer/float (#2423)
    • Add [CoreMonitorBundle] for [FPU] floating point registers (#2538, #2541, #2546, #2589)
  • [FPU] Zfh extension, option for Half-Precision unit (#2723)
    • replaces singleIn and singleOut with typeTagIn and typeTagOut
  • preliminary RV32Zfh extension support (#2359)
  • [RVV] -> 0.9 -> 1.0 (#2477, #2484, #2396, #2552, #2576)
    • Fractional LMUL
    • Tail-agnostic/mask-agnostic bits
    • EEW loads/stores
    • Some encoding changes
    • tighten fractional LMUL-SEW constraint
    • Instructions: add new and update RISC-V vector extension opcodes
    • reorder fields in vtype
  • add B extension opcodes and object model description (#2678)
  • fixed an issue where multiplierIO was unclonable (#2331)

Devices

  • [PLIC] add support for PLIC elaboration even when nDevices == 0 (#2351)
  • [PLIC] fix off-by-one for priority register description (#2718)
  • [BuildInDevices] introduce case class parameters to Zero and Error device #2684
    • make instantiation of buffers optional
    • allow for optional instantiation of CacheCork
  • [BasicBusBlocker] convert to chisel3, add scala-doc, add factory companion object (#2630)
  • [PhysicalFilter] added scaladoc and RegFieldDesc (#2685)
  • [BEU]
    • added a Device Tree description for the bus error unit (#2373)
    • report Corrupt+Denied on I-Fetch (#2482)

PRCI

  • [ResetSynchronizer][ClockGroupResetSynchronizer] add a pair of diplomatic reset synchronizers (#2666)
    • replaced IdentityNodes with AdapterNodes (#2689)
  • wrap Tiles in PRCI Domains (#2550)
    • contains logic related to power, reset, clock, and interrupt
  • define ResetCrossingType and use with BlockDuringReset in TilePRCIDomain (#2641)
    • analogous to ClockCrossingType. Currently, there are two crossing types: NoResetCrossing and StretchedResetCrossing(cycles: Int)
    • introduces Blockable util
  • Synchronizer primitive changes (#2212)
    • introduction of ClockCrossingReg
    • _SynchronizerShiftReg requires synchronizer depth > 1
    • deprecate IntXing and IntSyncCrossingSink
    • deprecate SyncResetSynchronizerShiftReg
  • [SynchronizerPrimitiveShiftReg] correct the dedup behavior for the *ResetSynchronizerPrimitiveShiftReg so you only end up with one copy (#2547)
  • add partial multiple reset scheme support (#2375)
  • AsyncResetReg: use chisel3 async resets (#2397)
  • Async Reset support for Atomics, FPU, and TLBroadcast (#2362)
  • [ResetStretcher][PRCI] add reset stretcher for Async Reset systems (#2566)
  • ClockGroupDriverParameters: allow for a configurable drive function for driving asynchronous clock groups with IO other than the implicit clock (#2319)
  • [ClockDivider] fixed bug where clock divider's source and sink functions always divided by two (#2610)
  • [InterruptBusWrapper] update synchronizer API #2640
    • replaces using IntXing in a synchronize method with to and from methods
    • this is to ensure synchronized registers are always put in the destination clock domain

Tile

  • [notification] provide reset values for cease and wfi (#2449)
  • [notification][CSR] Block wfi, halt, cease, and other valid signals during asynchronous reset (#2611)
    • trace.valid of CSR changed to async-reset delay (#2613)
  • [notification][WFI] expose WFI from core (#2315)
  • [i$] fixed bug where cease signal was asserted before potential glitching in I$ clock finished. Add an assertion to cease signal. (#2419, #2420, #2456)
  • [PMP][DTS] add pmp granularity to DTS (#2661)
  • [NMI] introduce non-maskable interrupt implementation (#2711)
  • val tiles in trait HasTiles is now populated eagerly via the TilesLocated Field. (#2504)

Subsystem

  • [HasTiles] add seipNode (#2665)
  • Topology changed from static traits to CDE-based configurable runtime (#2327)
    • HasHierachicalBusTopology trait replaced with two config options:
      • WithCoherentBusTopology
      • WithIncoherentBusTopology
  • renamed attachment API to location API (#2330)
  • [BundleBridge] to propagate [TileInputConstants]. ROM attachment changes (#2521 merged as #2531)
    • HasPeripheryBootROM and HasPeripheryBootROMModuleImp are removed and replaced by a call to BootROM.attach
    • BootROMParams Field is removed and replaced with BootROMLocated Field
    • MaskROMLocated Field is added
    • SubsystemExternalResetVectorKey, SubsystemExternalHartIdWidthKey and InsertTimingClosureRegistersOnHartIds Fields are added
    • Unused ResetVectorBits Field is removed
    • HasExternallyDrivenTileConstants bundle mixin is removed
    • HasResetVectorWire subsystem trait is removed
    • HasTileInputConstants and InstantiatesTiles subsystem traits are added
    • BaseTile exposes val hartIdNode: BundleBridgeNode[UInt] and resetVectorNode: BundleBridgeNode[UInt] and these are automatically connected to in HasTiles.
    • rocket.Frontend, rocket.ICache, rocket.DCache, rocket.NDCache now have BundleBridgeSink[UInt] for their reset vector or hartid wire inputs.
      • If you instantiate them manually, i.e. not using the traits e.g. rocket.HasHellaCache, you will have to manually connect up those nodes to the aforementioned BaseTile nodes.
    • follow up PR - bug fix for HartID and ResetVector width calcluation (#2543)
  • add HierarchicalLocation to LocationAPI (#2346)
  • [RocketCrossingParams] relax type of master param to TilePortParamsLike (#2634)
  • [Subsystem] Miscellaenous subsystem bus crossing changes (#2724)
    • introduce keys for bus crossings
    • allow for disabling of DriveClockFromMaster behavior
    • introduce MBus crossing to CoherentBusTopology
  • [Subsystem][PLIC] avoid using implicit clock (#2719)
  • Add an optional TileInputConstant as an MMIO Address Prefix used in ITIM and DTIM hit calculations (#2533)
    • follow-up: fix traceCoreNode duplication issue (#2561)

stage, linting, transforms

  • [stage] Fix a bug where unserializable RocketTestSuiteAnnotations were being serialized (#2424)
  • [stage] Fix a bug where the desired output file name was being superseded by another phase (#2424)
  • [RocketChipStage] Remove emitVerilog, emitFirrtl, and emitChirrtl methods from RocketChipStage (#2481)
  • [stage] expose Stage's --target-dir to Config (#2725)
  • [Transforms][Lint] add RenameDesiredNames transform and LintConflictingModuleNames Lint rule (#2452)
    • also adds RenameModulesAspect that can be used to emit name overrides and a LintConflictingModuleNamesAspect to collect DesiredNameAnnotations to be checked by the lint pass.
  • [ElaborationArtefactAnnotation] add ElaborationArtefactAnnotation - an API similar to ElaborationArtefacts (#2727)
    • this API is for assuring metadata has correct instance paths and signal names
    • allow renames to multiple targets for MemoryPathToken (#2729)

Debug

  • mcontext and scontext CSRs for breakpoint qualification (#2588)
  • allow a fast debugger reading dmstatus in a single dminner clock cycle to read the proper value (#2412)
  • fix address sent from DM to SB2TL (#2559)
  • add bus blocker to deny requests to dmInner when dmactive = 0 (#2205)
  • DMIToTL: remove PutPartial (#2598)
  • convert registers and wires from a Regs of Vector to Regs of UInt (#2597)
  • make instantiation of reset synchronizers optional (#2626)
  • allow DM at base address other than 0 (#2649)
  • [Periphery] workaround an autonaming bug with debug (#2657)
  • make nExtTriggers a val for compatibility with cloneType (#2667)
  • [BPWatch] have the watchpoint compare to store or load instruction type for matching (#2317)

AMBA, Tilelink

  • combine modifiable and cacheable, add read and write alloc fields (#2386)
  • [AXI4Deinterleaver][AXI4IdIndexer][AXI4UserYanker][TLToAXI4][Anotations] (#2676)
    • Scala doc
    • Clarifying comments
    • Unify TLToAXI4 metadata code paths into a single path through TLtoAXI4IdMap
    • Make any value of TLToAXI4.stripBits other than 0 illegal and stop using it internally.
    • Remove usage of un-consumed Annotated.idMapping and delete associated application and annotation class.
  • [AXI4Deinterleaver] support asynchronous reset (#2479)
  • [AXI4Deinterleaver] add buffer when optimized away (#2642, #2652)
  • [AXIS] allow masters to carry resources (#2443)
  • [SRAM] accomodate address ranges that require more than 32 bits #2491
  • [SRAM] Add public accessors for SRAM modules #2646
  • [SimAXIMem] introduce base address argument to constructor #2628
  • [TLRAM] improved cycle time for designs involving TLRAM #2582
  • TLMonitors: formal verification support and additional constraints
  • TLEdge: add require failure messages for TL edges (#2313)
  • minor tilelink v1 parameter fixes for setName and probe rendering (#2428)
  • [TLParameters] add v2 constructors (#2532)
  • [TLParameters] functions to look at emits parameters (#2572)
  • [Parameters] replace cover function with mincover (#2571)
  • [APBToTL] only assert address alignment when data is ready and valid on a-channel (#2314)
  • [TLBroadcast][TLSourceShrinker][TLCacheCork][SBA][$] Drive or pass through TL user bits (#2457, #2448, #2383, #2446)
  • [TLBroadcast] add API to create Probe filters for Broadcast coherence manager (#2509)
  • [TLBroadcast] fixed a Generator bug when instantiated with no inner cache (#2516)
  • [TLBroadcast] Add control parameters for control interface (#2519)
  • make it possible to filter with Banked Broadcast Hub (#2545)
  • [TLSourceShrinker] preserve meta data when no shrinkage is required (#2466)
  • [TLFragmenter] ensure Fragmenter raises corrupt signal when raising denied (#2468)
  • [Tilelink][Arbiter][Xbar][ReadyValidCancel] Add new API that replaces valid with earlyValid and lateCancel to fix a timing path for A-channel requests (#2480, #2488)
  • [TLCacheCork] prevent cache block write size from exceeding read size (#2527)
  • [TLCacheCork] switch CacheCork class to take a case class parameter (#2684)
    • with backwards compatible constructor in helper object
  • [TLBundle] C channel now has same user bits as A channel (#2632)
    • caches now responsible for driving AMBAProt on C-channel.
  • [TLArbiter] add highestIndexFirst arbitration policy (#2587)
  • [AHBToTL] retain AHB hrdata even during error response (#2512)
  • [AHBToTL] fix spurious fire of assertion on first cycle (#2523)
  • [CreditedIO] introduce new DecoupledIO interface for credit debit buffers (#2555)
  • [IdMap][IdMapEntry] standardize IdMap and IdMapEntry (#2483)
    • [AXI4IdIndexer] later fixed a bug with graphml parsing metadata bracketed in "< >" (#2638)
  • [IdMapEntry][OMIdMapEntry] add maxTransactionsInFlight field #2627

Diplomacy

  • versioning support for tilelink parameters (#2320)
  • allow users to access Lazy Module nodes (#2301)
  • JunctionNodes now support configurable up/down ratio (#2430)
  • dynamic and remote order: fix QoR in designs with large physical address maps (#2461)
  • [AddressSet] fix a bug where duplicated AddressSets would cause incorrect widening when unify is called. (#2502)
  • [LazyModule]
    • mark LazyModules for inlining such as nodes with circuit identity (inputs are outputted unchanged) (#2579)
      • inline xbar patch: (#2639)
    • add scaladoc (#2311)
  • Added more debug info to node requires (#2577)
  • [Nodes] documentation for Nodes (#2604)
  • [Nodes] replace bundleSafeNow guard with instantiated guard (#2680)
  • tutorial for adder (#2615)
  • [aop][Select] add Select Library API (#2674)
  • [DTS] allow node names up to 48 bytes (#2570)
  • [AddressAdjuster] and RegionReplicator now work on prefixes (not chip id) (#2430)
    • removes MultiChipMaskKey
  • [AddressAdjuster] patches (#2470)
    • user can now supply a default local base address for reporting manager address metadata other than the 0th region
    • let local and remote legs have different user bits using <:= operator
    • allow for no fifo ordering on the replicated region
    • more verbose requires
  • [BundleBridge] generalize BundleBroadcast into BundleBridgeNexus (#2497)
    • user can now supply input and output functions
  • [BundleBridge] add SafeRegNext to BundleBridgeNexus to preserve width (#2520)
  • [BundleBroadcast] add register pipelining argument (#2431)

Object Model

  • [OMMemoryMap] require register map to only go to one memory region (#2496)
  • [OMErrorDevice] added to Object Model (#2410, #2411)
  • added IdRange, IDMap to include source ids in object model (#2495)
  • added L2UTLB entries and memory (#2606)
  • [OMISA] Add OMVectorExtension.vstartALU field (#2578)
  • [RegFieldDesc]
    • add AddressBlocks for RegFieldDesc (#2437)
    • require RegFieldDesc to match RegEx to limit to a subspect of IP-XACT standard (#2525)
  • updates for AHB and AXI (#2427)
  • add Zfh extension (#2581)

Utilities, QoL, Other

  • make RC more tolerant to x-prop (#2659)
  • [util][rotate] fix rotate for zero-width wires (#2663)
  • [SimJTAG][SimDTM] fix a verilator bug due to delay statements (#2635)
  • register coverage now generated based on access type (#2384)
  • [BundleMap] improved API for user bits
    • Customizable field unification, Default for bulk assignments, Field and Key class required (#2318)
    • Use BundleMap for AMBA protocols (#2326)
    • various bug fixes to TL user fields (#2335)
  • [FixChisel3] Added some scaladoc commentary to the operators :<>, :<=, :=> to explain what they do and the rationale for their creation. (#2339)
  • [util] Add utilities for bitwise shifts by signed shift amounts (#2477)
  • [TLBusWrapper] more stability to internal wire names (#2515)
  • [LazyRoCC] convert LazyRoCC to chisel3 (#2553)
  • [OptimizationBarrier] give the module a name in generated verilog (#2507)
  • add test enable pin to Clock Gate (#2087)
  • [RecordMap] addd as an API for better diplomatic IO naming #2486
    • used to get easier to follow Clock Group signal names #2528
  • [IDPool] enable ResetAsynchronous Full (#2568)
  • [IDPool] add lateValid and revocableSelect to shift the deep logic cones from before the valid/selec registers to after the bitmap register (#2673, #2677)
  • [IDPool] infer widths (#2679)
  • Make AsyncValidSync a RawModule (#2352)
  • compiler warning fixes (#2357, #2356, #2355, #2354, #2353, #2378, #2379, #2380, #2442, #2567, #2757, #2758)
  • [SCIE] fix width mismatch assignment lint warning from VCS (#2563)
  • Initial scalatest flow support and aspect generation (#2309, #2517)
  • [linting] add Chisel Linting Framework (#2435)
  • [scalafix] enable scalafix and remove unused imports (#2648)
    • This requires downstream projects using rocket-chip's build.sbt to enable scalafix.
    • enable LeakingImplicitClassVal (#2650)
    • enable ProcedureSyntax (#2651)
  • mdoc infrastructure (#2615)
  • [PlusArg]
    • support for no-default PlusArgs and string-valued PlusArgs (#2453)
    • fix VCS lint warning for plusarg default bit width (#2558, #2562)
  • decode: improve runtime (#2462)
  • Switch to using Github Actions (#2465, #2472, #2530, #2536)
  • Some Travis changes were made, but travis is dropped in later releases (#2451, #2454, #2455, #2490)
  • Add scalatest to a bucket for regression testing (#2511)
  • RTLSim trace log:
    • fixed an issue where the wrong destination register being dumped in the RTLSim trace log (#2409)
    • enhanced log so only registers read or written are printed (#2414)
  • add CONTRIBUTING.md (#2342, #2473)
  • [wake]
    • add self-location rules (#2526)
    • fix string interpolation of bootrom path (#2535)
    • publish location of ivydependencies.json (#2540)
    • update CI to 0.19.0 (#2594 superseding #2584)
    • avoid hardcoded directory path for hardfloat repo #2633
  • [mill] add mill build system (#2654)
  • [sbt] remove jgit-repo resolver (#2364)
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